KR920004398B1 - A system and a method for setting memory structure by firmware automatically - Google Patents

Abstract

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Description

Memory configuration setting system and method for automatically setting memory configuration by firmware

1A and 1B are block diagrams showing one embodiment of a personal computer including the display configuration setting system of the present invention.

FIG. 2 shows the structure of the memory card RAS control register 100 in the embodiment shown in FIG.

3 is a diagram showing a relationship between an extended memory size and a value to be set in the memory card RAS control register 100. FIG.

4 is a flowchart showing the operation in the embodiment shown in FIG.

5A to 5F are timing diagrams when writing memory data, FIG. 5A is data output from the CPU, 5b is address output from the CPU, 5c is write signal output from the CPU, and 5d And 5e denotes a row address strobe (RAS) and a column address strobe (CAS) signal output from the memory controller, respectively, and an ACK signal indicating completion of recording from the memory controller 5f or 5f. Figure shown.

* Explanation of symbols for main parts of the drawings

11: CPU 12, 14: data bus

13, 14: latch circuit 16: system bus

19: cache memory 21: timing controller

22: bus controller 23: cache memory controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory configuration system for use in a computer system such as a personal computer, a personal workstation, and the like having a memory expansion mechanism having a plurality of memory expansion slots.

In recent years, with the rapid development of microprocessors, various personal computers and personal workstations have been developed, some of which have memory expansion mechanisms having a plurality of memory expansion slots. In a computer equipped with such a memory expansion mechanism, a method of setting a memory has conventionally been performed as follows.

That is, in the first method, a dip switch is provided on each of the expansion memory cards (boards), and the address and the memory size are set manually by operating this switch for each of the built-in expansion memory cards.

In the second method, a memory configuration was set by providing a unique signal line indicating a built-in state in each of the expansion memory cards.

However, any of the memory configuration setting methods in the conventional memory expansion mechanism has the drawback that the configuration becomes complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a simple and reliable memory configuration setting system by eliminating the complexity of hardware for setting the memory configuration.

In order to achieve the above object, according to the first aspect of the present invention, a memory configuration setting system includes: a memory expansion mechanism having a plurality of memory expansion slots; Recognition means for outputting a row address strobe signal to the plurality of memory expansion slots in a predetermined order and recognizing whether or not a memory is embedded in each slot; Holding means for holding a memory built-in state recognized by said recognition means; Means for determining whether to access each slot by referring to said holding means at the time of access of said memory expansion mechanism.

According to the second aspect of the present invention, a memory configuration setting method in a memory expansion mechanism having a plurality of memory expansion slots includes a row address strobe signal in a predetermined order to the plurality of memory expansion slots. Outputting and recognizing whether a memory is embedded in each slot; Maintaining a memory built-in state recognized in the recognition step; Determining whether to access each slot by referring to the held memory built-in state when the memory expansion mechanism is accessed.

According to the present invention, there is provided a computer system comprising a memory expansion mechanism comprising a plurality of memory expansion slots, comprising: means for outputting a RAS signal in a predetermined order to each slot, and recognizing a built-in state of the memory for each slot; There is a register which holds the in-memory state recognized by this means. As a result, a reliable memory configuration setting mechanism is realized with a simple configuration without requiring hardware such as signal lines and switches for memory configuration recognition.

1A and 1B are block diagrams showing one embodiment of a personal computer including the display configuration setting system of the present invention.

1A and 1B, reference numeral 11 denotes a central processing unit (CPU) for controlling the entire system. The CPU 11 outputs a row address strobe (RAS) signal. Reference numeral 12 denotes a 32-bit wide data bus (D31-24, D23-16, D15-8, D7-0). Reference numeral 13 denotes a latch circuit B-LAT for latching data on the data bus 12. The B-LAT 13 latches the RAS signal output from the CPU 11. Reference numeral 14 denotes a 32-bit wide memory bus (MD31-24, MD23-16, MD15-8, MD7-0). Reference numeral 16 denotes a system bus configured as 16-bit wide and 7-bit wide address buses SA19-0 and LA23-17 and 16-bit wide data buses SD15-8 and SD7-0 16a. Reference numeral 15 denotes a latch circuit C-LAT for latching address data on address buses SA19-0 and LA23-17 and data on data buses SD15-8 and SD7-0 16a. Reference numerals 17 and 18 denote internal RAMs, which are composed of dynamic random access memory (DRAM), respectively, and are battery-backed up. Reference numeral 19 denotes a cache memory, and reference numeral 20 denotes an internal ROM (BIOS-ROM) that stores a basic input and output system program (BIOS).

The internal RAM 17 is provided with a plurality of memory expansion slots (here, for convenience of description, consisting of three slots of slot A, slot B, and slot C), and each slot is shown in FIG. An expansion memory card of a predetermined form (memory capacity) is built into each slot as shown. That is, a memory card of 2MB (megabyte) in slot A, 2MB4MB / 8MB in slot B, and 2MB / 4MB in slot C is selectively installed.

Reference numeral 21 denotes a timing controller TC in charge of timing control of the entire system including the memory controller. Reference numeral 22 denotes a bus controller BUS-CNT which controls the system bus 16. Reference numeral 23 denotes a cache memory controller CMC which controls the cache memory 19.

Reference numeral 30 denotes a display control function for driving a CRT display at a high resolution (720 dots in the horizontal direction) and a multilevel tank (64 sea tanks), and simultaneously driving a CRT display and a plasma display (in this case, each display load display resolution Is a high-resolution display system (HRGS) having a display control function of 640 dots in the horizontal direction), and has a configuration arbitrarily connected to the apparatus main body. The CRT display is arbitrarily connected to the high resolution display system 30 through the connector C1. Reference numeral 31 denotes a plasma display (PDP). The display system 31 is connected to the plasma display PDP through the connector C2. The plasma display PDP is a standard equipment, and is normally connected to the connector C2.

Reference numerals SL1 and SL2 denote expansion slots SLOT-B and SLOT-C which allow connection of various expansion boards including display adapter boards.

FIG. 2 is a diagram showing the structure of the memory card RAS control register 100 in the embodiment shown in FIG. In Fig. 2, 2 bits 7 indicate bits ("0" = RAS signal output prohibited, "1" = RAS signal output permission) for outputting to the connector of slot A to control the RAS signal. Bits 5 and 4 are bits that control the RAS signal by outputting to the connector of slot B ("0" = RAS signal output prohibited, "0, 1" = 4MB-6MB permission for RAS signal output when accessing address memory, "1) , RAS signal output permission when address access of 0 "= 4MB-8MB, RAS signal output permission when address memory access of" 1,1 "= 4MB-12MB). Bits 3 and 2 are output to the connector of slot C to control the RAS signal ("0, 0" = RAS signal output prohibited, "0, 1" = 6MB-8MB, RAS signal output permission when accessing address memory, "1, 0" = RAS signal output permission when accessing address memory of 8MB-12MB, "1, 1" = RAS signal output permission when accessing memory of address of 12MB-14MB).

3 is a diagram showing a relationship between an extended memory size and a value to be set in the memory card RAS control register 100. FIG. The data set to the memory card RAS control register 100 is executed in accordance with the flowchart shown in FIG. At this time, under the control of the CPU 11, the area check of the expansion memory is performed by a predetermined processing routine immediately after the power is turned on. The shank outputs the RAS signal sequentially from slot A according to the flow chart of FIG. 4 to determine whether the memory is connected by writing or reading data, and according to the determination result, bit 7, of the memory card RAS control register 100 is determined. Values as described above are set to 5, 4, 3, and 2, respectively.

Hereinafter, operation of an embodiment of the present invention will be described in detail with reference to the flowchart of FIG.

In step 51 of Fig. 4, the CPU 11 determines whether or not an expansion memory card of 2MB is connected to the A connector. Specifically, the CPU 11 sends a test data signal shown in FIG. 5A, an address signal shown in FIG. 5B, and a write signal shown in FIG. 5C to the memory controller (not shown) via the A connector. In response to these signals, the memory controller outputs the RAS signal shown in FIG. 5D and the CAS signal shown in FIG. 5E to a memory connected to the A connector. As a result, the test data shown in FIG. 5A is recorded in the memory connected to the A connector. The memory controller then returns an ACK signal indicating completion of recording to the CPU 11. Next, similarly, the RAS signal, the address signal, and the read signal are sent to the A connector to read the recorded test data. If the recorded test data is read out, it can be determined that the memory card is connected to the A connector. The determination of which MB memory card is connected is performed by reading and writing by designating an address in the vicinity thereof. If 2MB of expansion memory is connected to the connector A in step 51, the CPU 11 sets " 1 " to bit 7 of the memory card RAS control register 100 in step 53. Next, in step 53, the CPU 11 determines which MB of expansion memory is connected to the connector. If an 8 MB memory card is connected, the CPU 11 proceeds to step 59 to set "1" to bit 4 and "1" to bit 5 of the memory card RAS control register 100, respectively. Next, in step 61, it is determined whether the expansion memory of the C connector 2MB is connected. If the connection is made in step 61, the CPU 11 sets " 1 " to bits 2 and 3 of the memory card RAS control register 100, respectively, in step 63. FIG. On the other hand, in step 61, if no connection is made, the process goes to step 79.

When it is determined in step 57 that the 4MB memory card is connected, the CPU 11 goes to step 65 to set "0" to bit 4 and "1" to bit 5 of the memory card RAS control register 100. . Next, in step 67, it is determined whether or not the 4MB extended memory is connected to the C connector. If the connection is made in step 67, in step 69, " 0 " is set in bit 2 of the memory card RAS control register 100 and " 1 " On the other hand, if it is determined in step 67 that no connection is made, the CPU 11 performs step 79.

In step 57, when it is determined that the memory card of 2MB is connected, the CPU 11 performs step 71, and " 1 " to bit 4 and " 0 " to bit 5 of the memory card RAS control register 100. Set it. Next, in step 73, if connected, the CPU 11 sets "1" to bit 2 and "0" to bit 3 of the memory card RAS control register in step 75. On the other hand, if it is determined in step 73 that it is not connected, the CPU 11 performs step 79.

When it is determined in step 57 that the memory card is not connected, the CPU 11 performs step 77 and sets " 0 " to bits 5 and 4 of the memory card RAS control register, respectively. Next, in step 79, " 0 " is set in bits 2 and 3 of the memory card RAS control register, respectively.

Claims (2)

A memory expansion mechanism having a plurality of memory expansion slots; Recognition means for outputting a row address strobe signal to the plurality of memory expansion slots in a predetermined order, and recognizing whether a memory is built in each slot; Holding means for holding a memory built-in state recognized by said recognition means; And a means for determining whether to access each slot by referring to said holding means at the time of access of said memory expansion mechanism. A memory configuration setting method of a memory expansion mechanism having a plurality of memory expansion slots, comprising: outputting a row address strobe signal in a predetermined order to the plurality of memory expansion slots, and for each slot, Recognizing built-in; Maintaining a memory built-in state recognized in the recognition step; And determining accessibility of each slot by referring to the maintained memory built-in state when the memory expansion mechanism is accessed.

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