JPS56143060A - Self-diagnosis for digital input circuit - Google Patents
Self-diagnosis for digital input circuitInfo
- Publication number
- JPS56143060A JPS56143060A JP4636280A JP4636280A JPS56143060A JP S56143060 A JPS56143060 A JP S56143060A JP 4636280 A JP4636280 A JP 4636280A JP 4636280 A JP4636280 A JP 4636280A JP S56143060 A JPS56143060 A JP S56143060A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- cpu
- input
- signal
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/273—Tester hardware, i.e. output processing circuits
- G06F11/277—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault-free response
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
PURPOSE:To make an input printed board self-monitored all the time and to prevent mis-outputs, by providing the input circuit with the memory section storing the test data signal from CPU for processing. CONSTITUTION:When the address through the address bus 10 from CPU judges the device of itself with the receiver 2 and decoder 4, the logical product signal with the OUT signal from the receiver 3 is input to the memory section 5. The memory 5 fetches one of the circuit test signals from the data bus 11, opens the gate of the memory 6 and reads in the test data from CPU to the memory 6. The memory 6 transmits this data to each photocoupler 7 of input circuits ID1-IDn and outputs to the line driver 1 via the amplifier. Input is made to the driver 1 via NAND2, and the gate is open with the signal from the receiver 3 and decoder 4, and the signal from the circuits ID1-IDn is fed to CPU via the bus 11. CPU compares the test data transmitted before with the data from the circuits ID1-IDn and if they are different, they are judged as failure and alarm is output.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4636280A JPS56143060A (en) | 1980-04-09 | 1980-04-09 | Self-diagnosis for digital input circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4636280A JPS56143060A (en) | 1980-04-09 | 1980-04-09 | Self-diagnosis for digital input circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56143060A true JPS56143060A (en) | 1981-11-07 |
Family
ID=12745034
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4636280A Pending JPS56143060A (en) | 1980-04-09 | 1980-04-09 | Self-diagnosis for digital input circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56143060A (en) |
-
1980
- 1980-04-09 JP JP4636280A patent/JPS56143060A/en active Pending
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