JPS6469975A - Logic operation circuit package - Google Patents

Logic operation circuit package

Info

Publication number
JPS6469975A
JPS6469975A JP62227625A JP22762587A JPS6469975A JP S6469975 A JPS6469975 A JP S6469975A JP 62227625 A JP62227625 A JP 62227625A JP 22762587 A JP22762587 A JP 22762587A JP S6469975 A JPS6469975 A JP S6469975A
Authority
JP
Japan
Prior art keywords
circuit
fault
signal
pseudo
impressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62227625A
Other languages
Japanese (ja)
Inventor
Kenji Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62227625A priority Critical patent/JPS6469975A/en
Publication of JPS6469975A publication Critical patent/JPS6469975A/en
Pending legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To enable the execution of a detailed pseudo fault in a short verification time on the basis of a pseudo fault diagnosis information, by providing a decoder decoding the information inputted from outside, a hold circuit storing an output of the decoder temporarily and a logical product circuit outputting the logical product of a part of an input signal of a logic operation circuit and an output signal of the hold circuit. CONSTITUTION:A pseudo-fault diagnosis input signal 10 impressed from an external control unit is impressed on a decoder circuit 9, and a pseudo fault signal 8 for a desired corresponding position (either one of input signals 2-2) is outputted by this circuit. The signal 8 is inputted to a hold circuit 7 conducting temporary storage, and an output 6 thereof is held and then impressed on each corresponding logical product circuit 3. When a package 11 including a logic operation circuit 1 is made to execute a testing diagnosis of various fault detecting circuits provided in the circuit 1 and when each diagnostic program prepared for a fault of the circuit 1 is executed or verified, according to this constitution, the setting of a pseudo fault for the package 11 is enabled by impressing the desired signal 10 from the external control unit under the condition that the circuit 1 executes an ordinary operation.
JP62227625A 1987-09-10 1987-09-10 Logic operation circuit package Pending JPS6469975A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62227625A JPS6469975A (en) 1987-09-10 1987-09-10 Logic operation circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62227625A JPS6469975A (en) 1987-09-10 1987-09-10 Logic operation circuit package

Publications (1)

Publication Number Publication Date
JPS6469975A true JPS6469975A (en) 1989-03-15

Family

ID=16863854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62227625A Pending JPS6469975A (en) 1987-09-10 1987-09-10 Logic operation circuit package

Country Status (1)

Country Link
JP (1) JPS6469975A (en)

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