JPS55115754A - Output selection circuit - Google Patents
Output selection circuitInfo
- Publication number
- JPS55115754A JPS55115754A JP2292279A JP2292279A JPS55115754A JP S55115754 A JPS55115754 A JP S55115754A JP 2292279 A JP2292279 A JP 2292279A JP 2292279 A JP2292279 A JP 2292279A JP S55115754 A JPS55115754 A JP S55115754A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- output
- rom
- output selection
- selection circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
Abstract
PURPOSE:To perform the output selection by using ROM for the selective condition forming circuit and corresponding the selection signal inputted to ROM to the address, in the output selection circuit of duplicated cyclic data transmission unit. CONSTITUTION:Assuming that the both A and B systems are normal, the gate of the system A is open to the output and the data for the system A is present. In this state, if a failure is taken place to the system A and one of the selective conditions is ON, since the input address of ROM23 of the system A is changed, the output of ROM23 of the system A is ''0'' to close the gate of the gate 27 of the system A. ROM24 of the system B opens the gate of the gate 28 of the system B and the gate of the system is outputted to the output OUT if no failure in the system. This selective operation can be programmed in ROM depending on the selection signal and the priority.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2292279A JPS55115754A (en) | 1979-02-28 | 1979-02-28 | Output selection circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2292279A JPS55115754A (en) | 1979-02-28 | 1979-02-28 | Output selection circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55115754A true JPS55115754A (en) | 1980-09-05 |
Family
ID=12096129
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2292279A Pending JPS55115754A (en) | 1979-02-28 | 1979-02-28 | Output selection circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55115754A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58129855A (en) * | 1982-01-27 | 1983-08-03 | Nec Corp | Deciding circuit for pulse pattern normalcy |
-
1979
- 1979-02-28 JP JP2292279A patent/JPS55115754A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58129855A (en) * | 1982-01-27 | 1983-08-03 | Nec Corp | Deciding circuit for pulse pattern normalcy |
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