JPS5745653A - Multiplex output collation system - Google Patents

Multiplex output collation system

Info

Publication number
JPS5745653A
JPS5745653A JP55121082A JP12108280A JPS5745653A JP S5745653 A JPS5745653 A JP S5745653A JP 55121082 A JP55121082 A JP 55121082A JP 12108280 A JP12108280 A JP 12108280A JP S5745653 A JPS5745653 A JP S5745653A
Authority
JP
Japan
Prior art keywords
data
address
counter
registers
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55121082A
Other languages
Japanese (ja)
Inventor
Hiromasa Yamaoka
Yuzaburo Iwasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55121082A priority Critical patent/JPS5745653A/en
Publication of JPS5745653A publication Critical patent/JPS5745653A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G06F11/167—Error detection by comparing the memory output

Abstract

PURPOSE:To process the collation of multipoint data with one data collation set, by making collation through the readout of the content of registers which are accessible, and transmitting the coincidence data as the address for the counter value to the output device. CONSTITUTION:Data outputted from each duplex CPU(not shown) via buses 101, 102 are inputted to registers 51, 52. The write-in address of the data section is designated with the address of the buses 101, 102 and the readout address of data is designated with the value of a counter 53. The data of the registers 51, 52 designated with the counter 53 is collated 54, and only when they coincide, the data is outputted to a bus 103 by taking the value of the counter 53 as the address section. If uncoincidence of data has been observed for longer than a prescribed time, an error signal is transmitted.
JP55121082A 1980-09-03 1980-09-03 Multiplex output collation system Pending JPS5745653A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55121082A JPS5745653A (en) 1980-09-03 1980-09-03 Multiplex output collation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55121082A JPS5745653A (en) 1980-09-03 1980-09-03 Multiplex output collation system

Publications (1)

Publication Number Publication Date
JPS5745653A true JPS5745653A (en) 1982-03-15

Family

ID=14802407

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55121082A Pending JPS5745653A (en) 1980-09-03 1980-09-03 Multiplex output collation system

Country Status (1)

Country Link
JP (1) JPS5745653A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267140A (en) * 1985-05-21 1986-11-26 アルフレツド・テヴエス・ゲ−エムベ−ハ− Method and circuit for suppressing short-time interference
JP2007004690A (en) * 2005-06-27 2007-01-11 Hitachi Ltd Storage control method, system, and program

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61267140A (en) * 1985-05-21 1986-11-26 アルフレツド・テヴエス・ゲ−エムベ−ハ− Method and circuit for suppressing short-time interference
JP2007004690A (en) * 2005-06-27 2007-01-11 Hitachi Ltd Storage control method, system, and program
JP4531643B2 (en) * 2005-06-27 2010-08-25 株式会社日立製作所 Storage control method, system and program

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