JPS56138327A - Frequency multiple circuit - Google Patents
Frequency multiple circuitInfo
- Publication number
- JPS56138327A JPS56138327A JP4152580A JP4152580A JPS56138327A JP S56138327 A JPS56138327 A JP S56138327A JP 4152580 A JP4152580 A JP 4152580A JP 4152580 A JP4152580 A JP 4152580A JP S56138327 A JPS56138327 A JP S56138327A
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- fed
- delay circuit
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/00006—Changing the frequency
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To make small the occupied area in circuit integration, and to make uniform the pulse width of signal multiplied, by providing the binary counter counting the output of a delay circuit and taking exclusive logic between the input signal and the count value of a counter. CONSTITUTION:The input signal A is fed to one input of an exclusive logic circuit 21, the output of the circuit 21 is fed to the delay circuit 22 and logical sum circuit 23, the output of the delay circuit 22 is fed to the circuit 23 and also to the binary counter 24, and the output signal is sequentially output through inversion in synchronizing with the leading of the output. The output inverted with this counter 24 is fed to another input of the circuit 21. The circuit 21 is controlled with the output D phase-inverting the output C of the delay circuit 22, and the output E is output with the logical sum between the output B of the circuit 21 and the output C of the delay circuit 22. Further, the pulse width to be multiplied is made uniform and the occupied area in circuit integration can be reduced without providing clock generators.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152580A JPS56138327A (en) | 1980-03-31 | 1980-03-31 | Frequency multiple circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152580A JPS56138327A (en) | 1980-03-31 | 1980-03-31 | Frequency multiple circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56138327A true JPS56138327A (en) | 1981-10-28 |
| JPH0113653B2 JPH0113653B2 (en) | 1989-03-07 |
Family
ID=12610802
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4152580A Granted JPS56138327A (en) | 1980-03-31 | 1980-03-31 | Frequency multiple circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56138327A (en) |
-
1980
- 1980-03-31 JP JP4152580A patent/JPS56138327A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0113653B2 (en) | 1989-03-07 |
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