JPH0113653B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency multiplier circuit that multiplies the frequency of an input signal.

Integrated circuit devices for watches and small electronic computers that are constructed of complementary MOS transistors are now rapidly becoming multifunctional. Also, one of the multifunctional functions mentioned above is a melody generation function. This melody generation function is to obtain various frequency signals by dividing the clock signal of a predetermined frequency generated inside the integrated circuit device by changing the frequency division ratio according to a certain order, and then to obtain various frequency signals. A melody sound is generated by driving a piezoelectric speaker or the like. By the way, a collection of devices that require low power consumption, such as watches, to have the above-mentioned melody generation function.
Since the frequency of the clock signal that is constantly generated inside the integrated circuit device cannot be made higher than necessary (for example, 32.768KHz), the scale increments of the melody tones generated by using it as is will be insufficient. This causes the inconvenience that a high-quality melody sound cannot be obtained. For this reason, a frequency multiplier circuit is generally used to obtain a frequency twice that of the clock signal only when a melody tone is generated.

FIG. 1 is a circuit configuration diagram showing an example of the conventional frequency multiplier circuit described above, and as shown in the figure, for example,
Delay circuit 11 that delays input signal A of 32.768KHz
and an exclusive OR circuit (EXCLUSIVE-OR hereinafter referred to as EX-OR) 12 to which the output signal B of this delay circuit 11 and the input signal A are supplied in parallel.
It is composed of. In such a conventional circuit, the output signal C of the exclusive OR circuit 12 is as shown in the timing chart of FIG.
Since signal B is at a high level only during periods when the levels of signal B are different from each other, its frequency is twice that of signal A.

By the way, in order to obtain a predetermined pulse width as the signal C, it is necessary to provide a sufficient delay time in the delay circuit 11 as necessary. The delay circuit 11 is generally constructed by cascading a time constant circuit consisting of a resistor and a capacitor or inverters in multiple stages, so if the delay circuit 11 has a sufficient delay time, the area occupied by the frequency multiplier circuit in the integrated circuit device will be reduced. The disadvantage is that the larger the Another disadvantage is that the pulse width of the signal C is not uniform because the signal delay times at the rise and fall of the signal A of the delay circuit 11 are different.

This invention was made in consideration of the above-mentioned circumstances, and its purpose is to reduce the area occupied by an integrated circuit and to make the pulse width of the multiplied signal uniform. The purpose of the present invention is to provide a frequency multiplier circuit that provides the following.

Hereinafter, one embodiment of the present invention will be described with reference to the drawings. In Figure 3, input signal A is EX-OR
It is supplied to one input end of 21. Above EX-OR
The other input terminal of 21 receives an output signal D of a binary counting circuit (hereinafter referred to as a binary counter), which will be described later.
is supplied. The output signal B of the EX-OR 21 is supplied to one input terminal of a delay circuit 22 and an OR circuit (hereinafter referred to as an OR gate) 23. Further, the output signal C of the delay circuit 22 is supplied to the other input terminal of the OR gate 23. Furthermore, the signal C is supplied to the clock terminal of the binary counter 24. This binary counter 24 is designed to sequentially invert its output state in synchronization with the rise of the signal C, and its output signal D is supplied to the other input terminal of the EX-OR 21.
Further, the OR gate 23 outputs a signal E having twice the frequency of the signal A.

Next, the operation of the circuit configured as described above will be explained in the fourth section.
This will be explained using the timing chart shown in the figure.
First, let's start with the case where the output signal D of the binary counter 24 is also at a low level during the period when the signal A is at a low level.
The output signal B of 21 is at a low level. Therefore, at this time, the output signal C of the delay circuit 22 also becomes low level, and the output signal E of the OR gate 23 also becomes low level.
is also at a low level. Next, when signal A rises to a high level, signal B subsequently rises to a high level. When the signal B rises to a high level, the signal E subsequently rises to a high level. Further, when the signal delay time T _U at the rise of the input signal of the delay circuit 22 has elapsed after the signal B rises to a high level, the signal C rises. When the signal C rises, the signal D
rises to a high level. When the signal D rises to a high level, the input signals of the EX-OR 21 both become high levels, so that the signal B, which had been at a high level, falls to a low level. Furthermore, when the signal delay time T _D at the time of the fall of the input signal of the delay circuit 22 has elapsed after the signal B falls to a low level,
Signal C, which had been at a high level until now, falls.
When the signal C falls, the signal E, which has been at a high level, falls to a low level. Next, signal A, which has been at high level until now, falls to low level. At this time, the signal D is at a high level, and this circuit state is maintained as long as the signal A is at a high level. Now, in this state, when the signal A falls to a low level, the signal B subsequently rises to a high level. After the signal A rises, the signal E again rises to a high level. Further, as described above, when the signal delay time T _U at the rise of the input signal to the delay circuit 22 has elapsed after the signal B rises to a high level, the signal C rises to a high level. Further, when the signal C rises to a high level, the signal D is subsequently inverted to a low level. When the signal D is inverted and becomes a low level, both of the input signals of the EX-OR 21 become a low level, so that the signal B, which had been at a high level, falls to a low level. Furthermore, as described above, when the signal delay time T _D at the time of the fall of the input signal of the delay circuit 22 has elapsed after the signal B falls to the low level, the signal C, which had been at the high level until now, falls. Further, when the above signal falls, the signal E, which has been at a high level, falls to a low level again, and the signal D remains at a low level, returning to the initial state of the present invention. Therefore, it was shown that the same operation as described above is repeatedly performed in response to the rise and fall of signal A. As is clear from FIG. 4, the output signal E of the OR gate 23 has a frequency twice that of the input signal A, and this signal E is obtained as a multiplied signal.

Incidentally, in the above embodiment circuit, the pulse width of the signal E is the sum of the signal delay time T _U at the rise of the input signal of the delay circuit 22 and the signal delay time T _D at the fall of the input signal. Therefore, compared to the conventional case where one pulse of the multiplied signal is obtained by using the signal delay time at each rise or fall of the input signal of the delay circuit, the signal E
A delay circuit 22 for obtaining a predetermined pulse width as
It suffices if the signal delay time in is half that of the conventional one.
Therefore, the area occupied by the delay circuit 22 within the delay circuit device can be reduced compared to the conventional art.
Further, in the above embodiment circuit, only the OR gate 23 and the binary counter 24 are increased compared to the conventional circuit, and the delay circuit 22 occupies the largest area. Therefore, if the area of the delay circuit 22 can be reduced, the above embodiment can be implemented. When the example circuit is integrated into an integrated circuit, the area occupied can be reduced. Furthermore, the pulse width of the signal E is the signal delay time T _U of the delay circuit 22.
and T _D , so the pulse width of the signal E becomes uniform. Therefore, the circuit margin of the above embodiment circuit can be increased.

Note that the present invention is not limited to the above-described embodiment; for example, in the embodiment described above, the output signal state of the binary counter 23 is sequentially inverted in synchronization with the rising edge of the signal C;
This may be sequentially inverted in synchronization with the falling edge of the signal C.

As described above, according to the present invention, it is possible to reduce the area occupied when integrated into a circuit, and to provide a frequency multiplier circuit in which the pulse width of the multiplied signal is uniform.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram showing an example of a conventional frequency multiplier circuit, Fig. 2 is a timing chart showing its operation, Fig. 3 is a circuit configuration diagram showing an embodiment of the present invention, and Fig. 4 is its operation. This is a timing chart showing the following. 21...Exclusive OR circuit (EXCLUSIVE-
OR), 22...delay circuit, 23...OR circuit (OR gate), 24...binary counting circuit (binary counter).

Claims (1)

[Claims] 1. An exclusive OR circuit to which an input signal to be multiplied is supplied, a delay circuit that delays the output signal of this exclusive OR circuit, and an output signal state that is inverted by the rise of the output signal of this delay circuit. A frequency converter comprising a binary counting circuit to which the output signal is supplied to the exclusive OR circuit, and an OR circuit to which the output signals of the exclusive OR circuit and the delay circuit are respectively supplied. Multiplier circuit.