JPH0475690B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to semiconductor circuits, and more particularly, to semiconductor circuits.
This invention relates to a sweep oscillation circuit that can be applied to continuously change the frequency in a digital circuit controlled by a CPU.

Prior Art When obtaining a signal whose frequency changes continuously in a digital circuit controlled by a CPU, a programmable timer/counter IC is used to switch the frequency at fixed intervals by software (program). There is a method to do this, but this method has the problem of increasing the burden on the CPU and software.

Purpose The present invention aims to perform desired sweep oscillation using hardware without placing a burden on the CPU and software.

Configuration The configuration of the present invention will be described below based on specific examples. FIG. 1 is a block diagram showing the circuit configuration of the present invention, showing a sweep oscillation circuit in a semiconductor circuit having a CPU and capable of programmably setting predetermined data in a plurality of registers. Data related to sweep oscillation from the CPU is transferred to four registers 1 via data bus 11.
-4 are sent out and written to each register 1-4 by write signal 12. The output signal of the first register 1 is connected to an input of a shift register 5 and one input of an adder 6. The output signal of the shift register 5 is connected to the other input of the adder 6. The shift register 5 includes a shift number control section 2'
is shifted by the number of times set in the second register 2. Further, the adder 6 is controlled by the sign control section 3'.
Addition or subtraction is controlled depending on the contents set in the third register. Timer 8 is the fourth register 4
A switching signal is generated every set time, and the adder 6 executes addition (subtraction) at the timing of this switching signal. The output signal of the adder 6 is connected to the input of a counter 7, and the counter 7 counts the clock signal 9 from a reference oscillator (not shown) and outputs a pulse as the output signal 10 when the clock signal 9 becomes equal to the output value of the adder 6. One occurs.

Next, the operation will be explained with reference to the block diagram of FIG. 1 and the timing chart of FIG. 2. First, the initial value Ta ₀ of the pulse repetition period, the number of shifts n, the direction of change + or -, and the timer value Tb are set in the first to fourth registers by the CPU.
Timer 8 starts operating as a timer for Tb. At the same time, the shift register 5 is shifted by the number n set in the second register 2, resulting in 2 ⁿ
Division is performed. In addition, shift register 5
is initialized to all zeros at this stage, and therefore remains all zeros even after the shift. When a switching signal is output from the timer 8 after time Tb, the adder 6 changes the contents of the first register 1 to Ta ₀
and the contents of shift register 5, all zeros, are added. During this addition, if the sign set in the third register 3 is positive, addition is performed, and if it is negative, subtraction is performed. In this example, it is a positive sign. However, at this stage, the shift register 5 is all zero, so the output value of the adder 6 ends up being the initial value Ta ₀ of the repetition period. Next, the counter 7 counts the number of clock signals 9 until the output value Ta ₀ of the adder 6 is reached, and then generates one pulse as the output signal 10. Thereafter, the counter 7 continuously counts the clock signal 9 until it becomes equal to the output value _Ta0 of the adder 6 and generates one pulse. That is, as the output signal 10, the repetition period
A pulse train of Ta ₀ will be generated. On the other hand, an adder 6 is provided in the first register 1 and shift register 5.
The output value Ta ₀ of is newly loaded, and the shift register 5 is shifted n times. That is, the output signal 10
While a pulse train with a repetition period Ta ₀ is being generated, the contents of the first register 1 are updated to Ta ₀ and the contents of the shift register 5 are updated to Ta ₀ /2 ⁿ . Thereafter, when a switching signal is generated from the timer 8 after a period of Tb has elapsed, the adder 6 adds the content Ta ₀ of the first register 1 and the content Ta ₀ /2 ⁿ of the shift register to obtain an output value Ta ₁ =Ta ₀ +Ta Outputs _0/2 ⁿ . As a result, the counter 7 counts the clock signal 9 up to the updated output value Ta ₁ =Ta ₀ +Ta ₀ / ²ⁿ of the adder 6 and generates one pulse. That is, the output signal 10
After generating a pulse train with a repetition period Ta ₀ for Tb time, the repetition period is Ta ₁ = Ta ₀ +
Update Ta ₀ /2 ⁿ and generate a pulse train. Here, the output value Ta ₁ of the adder 6 is newly loaded into the first register 1 and the shift register 5, and the shift register 5 is shifted n times to become Ta ₁ /2 ⁿ .

By the way, since the timer 8 generates a switching signal every Tb time, the contents of the first register 1 and the shift register 5 are updated and added one after another. As a result, as shown in the output waveform diagram of Fig. 2, the output signal 10
The pulse repetition period of changes every Tb time, Ta ₀ = Ta ₀ Ta ₁ = Ta ₀ + Ta ₀ /2 ⁿ Ta ₂ = Ta ₁ + Ta ₁ /2 ⁿ 〓 Tam = Tan _-1 + Ta _n-1 /2 ⁿ , and a sweep oscillation in which the frequency changes one after another is obtained. In this example, the frequency gradually decreases,
By setting a negative sign in the third register 3,
It is also possible to gradually increase the frequency.

Effects According to the present invention, by simply setting data corresponding to the initial value of the frequency, the amount of frequency change, and the direction of change in the register, the desired sweep oscillation can be executed by hardware. When
The burden on the CPU and software can be almost eliminated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of the circuit of the present invention, and FIG. 2 is a waveform diagram of the output signal 10 in FIG. 1. Explanation of symbols, 1...First register, 2...Second
Register, 3... Fourth register, 4... Fourth register, 5... Shift register, 6... Adder, 7
... Counter, 8 ... Timer, 9 ... Clock signal, 10 ... Output signal.

Claims (1)

[Scope of Claims] 1. A first register for setting the repetition period of the periodic rectangular pulse train as the number of clock signals from the reference oscillator, and a shift for determining the amount of change in the repetition period by division by the shift of the first register. a second register that sets the number of times; a third register that sets a sign that determines whether the change in repetition period is positive or negative; and a fourth register that sets the time for which the pulse train continues to be generated in a constant repetition period; a shift register for shifting the contents of the first register by the number of times set in the second register; and a shift register for adding the contents of the first register and the shift register according to the sign set in the third register. a counter for counting the number of clock signal pulses from the reference oscillator according to the contents of the adder to generate a pulse train; and generating a switching signal at every time set in the fourth register. A sweep oscillation circuit comprising a timer that generates a signal.