JPS6111833Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a device for generating alarm sounds and the like using attenuated sounds. In contrast to conventional generators, which repeat a monotonous constant cycle, the present invention proposes a generator that generates an alarm sound not only by such a single-cycle attenuated tone sequence, but also by a combination of long and short attenuated tones. It is something to do. An embodiment of the present invention will be described below based on the drawings. FIG. 1 shows its structure, in which a clock pulse enters from an input terminal 1 and is applied to a flip-flop array 2 consisting of n flip-flops FF ₁ -FF _o connected in series. Although the logic circuit 5 is not necessarily required, the operation of the device is controlled by a clock pulse m.
This is for repeating every number (m<2 ⁿ ). That is, the flip-flop array 2 and the logic circuit 5 constitute an m-ary counter. The logic circuit 3 is a circuit that selectively outputs two or more types of pulses with a repetition period that is an integral multiple of the repetition period of the clock pulse, based on the combination of states of the flip-flops FF ₁ to FF _o of the flip-flop array 2 and the clock pulse. The sound generating circuit 4 generates an attenuated sound train based on the output pulse from the logic circuit 3 and the input from the audio frequency input terminal 6. As an example, according to FIG. 2, n=2, m=
Case 4 will be explained. The two flip-flops FF ₁ and FF ₂ operate as shown in b and c by the clock pulse a, but the truth table of the logic circuit 3 is
Assuming that the structure is as shown in the table, the output of the logic circuit 3 will be as shown in FIG. 2d. If the attenuated sound generation circuit 4 is driven by the attenuated sound generation circuit 4, an attenuated sound train consisting of a combination of long and short sounds as shown in FIG. 2e is obtained at the attenuated sound train output terminal 7.

[Table] As the attenuation sound generating circuit 4, for example, a circuit as shown in FIG. 3 is used. In FIG. 3, capacitor C is charged while the drive pulse of logic circuit 3 applied to terminal 8 is at High level, and terminal 8 is at Low level.
When the level is reached, the charge in the capacitor C is discharged through the resistor R. Therefore, the collector current of the transistor Tr is highest when the capacitor C is pulse-charged, and gradually decreases as the capacitor C is discharged. Therefore, since the gain of the transistor Tr also changes with the current, even if the signal level applied to the audio frequency input terminal 6 is constant, the output obtained at the collector becomes a damped sound controlled by the drive pulse. As described above, according to the present invention, an alarm sound can be generated not only by a single-period attenuated tone sequence but also by a combination of long and short attenuated tones.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a waveform diagram of each part, and FIG. 3 is a specific circuit diagram of the attenuated sound generating circuit. 1... Clock pulse input terminal, 2... Flip-flop array, 3... Logic circuit, 4... Attenuated sound generation circuit, 6... Audio frequency input terminal, 7... Attenuated sound string output terminal.

Claims (1)

[Scope of utility model registration request] A clock pulse source, a cascade-connected flip-flop array driven by the clock pulse, and two or more types of repetition periods that are integral multiples of the repetition period of the clock pulse depending on the combination of states of the flip-flops constituting the flip-flop array. a logic circuit that selectively generates pulses;
A damping sound generating device comprising a damping sound generating circuit driven by a pulse generated by the logic circuit.