JPS56110367A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPS56110367A
JPS56110367A JP1226180A JP1226180A JPS56110367A JP S56110367 A JPS56110367 A JP S56110367A JP 1226180 A JP1226180 A JP 1226180A JP 1226180 A JP1226180 A JP 1226180A JP S56110367 A JPS56110367 A JP S56110367A
Authority
JP
Japan
Prior art keywords
priority
control circuit
message
controller
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1226180A
Other languages
Japanese (ja)
Other versions
JPS6147460B2 (en
Inventor
Takane Kakuno
Mitsuhiro Ishizaka
Shigeo Nakatsuka
Tachiki Ichihashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1226180A priority Critical patent/JPS56110367A/en
Publication of JPS56110367A publication Critical patent/JPS56110367A/en
Publication of JPS6147460B2 publication Critical patent/JPS6147460B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To improve the responsibility to a transmission request of high priority, by providing the priority to the transmission request and giving priority for processing to the request in the order of higher priority. CONSTITUTION:The transmission request message is received from the communication controller CCU3 of the terminal device T2 by the line control circuit 2b. Then a comparison is given at the priority control circuit 3 between the priority PR within the control field of the reception transmitting frame and the priority under transfer. In case the PR of the reception data is higher than that of under transferring, this is informed to the line control circuit 2b from the priority control circuit 3. The circuit 2b transfers the received message to the memory 5 and then informs a reception of message to the common control circuit 4. The circuit 4 of the controller CCU1 reads the received message out of the buffer 5 and then decodes it, and then sends a message to the controller CCU2 of the terminal device T1 to indicate a temporary holding of the transmission of data to perform necessary process. After this, the transmission data is sent to the controller CCU2 which is held up to present.
JP1226180A 1980-02-04 1980-02-04 Communication controller Granted JPS56110367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1226180A JPS56110367A (en) 1980-02-04 1980-02-04 Communication controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1226180A JPS56110367A (en) 1980-02-04 1980-02-04 Communication controller

Publications (2)

Publication Number Publication Date
JPS56110367A true JPS56110367A (en) 1981-09-01
JPS6147460B2 JPS6147460B2 (en) 1986-10-20

Family

ID=11800423

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1226180A Granted JPS56110367A (en) 1980-02-04 1980-02-04 Communication controller

Country Status (1)

Country Link
JP (1) JPS56110367A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159497A (en) * 1984-08-31 1986-03-26 ヤマハ株式会社 Data communication equipment for electronic musical instrument
JPS63226151A (en) * 1986-10-15 1988-09-20 Fujitsu Ltd Multiple packet communication system
JPS63234343A (en) * 1986-12-22 1988-09-29 アメリカン テレフォン アンド テレグラフ カムパニー Communication between station of system of a plurality of processors linked to communication medium and a plurality of stations
JPH01241660A (en) * 1988-03-24 1989-09-26 Toshiba Corp Communication system between processor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6159497A (en) * 1984-08-31 1986-03-26 ヤマハ株式会社 Data communication equipment for electronic musical instrument
JPH0690616B2 (en) * 1984-08-31 1994-11-14 ヤマハ株式会社 Electronic musical instrument data communication device
JPS63226151A (en) * 1986-10-15 1988-09-20 Fujitsu Ltd Multiple packet communication system
JPS63234343A (en) * 1986-12-22 1988-09-29 アメリカン テレフォン アンド テレグラフ カムパニー Communication between station of system of a plurality of processors linked to communication medium and a plurality of stations
JPH0550021B2 (en) * 1986-12-22 1993-07-27 American Telephone & Telegraph
JPH01241660A (en) * 1988-03-24 1989-09-26 Toshiba Corp Communication system between processor

Also Published As

Publication number Publication date
JPS6147460B2 (en) 1986-10-20

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