JPS6429041A - Data transmission reception controller - Google Patents

Data transmission reception controller

Info

Publication number
JPS6429041A
JPS6429041A JP18438287A JP18438287A JPS6429041A JP S6429041 A JPS6429041 A JP S6429041A JP 18438287 A JP18438287 A JP 18438287A JP 18438287 A JP18438287 A JP 18438287A JP S6429041 A JPS6429041 A JP S6429041A
Authority
JP
Japan
Prior art keywords
data
station
addressed
stored
reception data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18438287A
Other languages
Japanese (ja)
Inventor
Kazufumi Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Business Innovation Corp
Original Assignee
Fuji Xerox Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Xerox Co Ltd filed Critical Fuji Xerox Co Ltd
Priority to JP18438287A priority Critical patent/JPS6429041A/en
Publication of JPS6429041A publication Critical patent/JPS6429041A/en
Pending legal-status Critical Current

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  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To receive data even while the data of its own station is being sent by storing the reception data in a saving and storing means for a while, when the reception data, addressed to its own station, is detected. CONSTITUTION:When the received communication data is addressed to its own station, the reception data is stored temporarily in a buffer memory 29 through a bus gate circuit 27. In this case, if the data is being transmitted from a main memory 31 to other station, at the point of time when the transmission of this data is finished, the reception data, stored in the buffer memory 29, is transferred to the main memory 31 through the bus gate circuit 30. Besides, when the reception data is addressed to other station as well, the reception data is stored in the buffer memory 29, and after the transmission of the data to be read out from the main memory 31 is finished, a data multiplexer 28 is made to select the data, stored in the memory 29 and addressed to other station, and the data is transmitted through a transmission circuit 22.
JP18438287A 1987-07-23 1987-07-23 Data transmission reception controller Pending JPS6429041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18438287A JPS6429041A (en) 1987-07-23 1987-07-23 Data transmission reception controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18438287A JPS6429041A (en) 1987-07-23 1987-07-23 Data transmission reception controller

Publications (1)

Publication Number Publication Date
JPS6429041A true JPS6429041A (en) 1989-01-31

Family

ID=16152211

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18438287A Pending JPS6429041A (en) 1987-07-23 1987-07-23 Data transmission reception controller

Country Status (1)

Country Link
JP (1) JPS6429041A (en)

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