JPS57176861A - Terminal equipment - Google Patents

Terminal equipment

Info

Publication number
JPS57176861A
JPS57176861A JP56061176A JP6117681A JPS57176861A JP S57176861 A JPS57176861 A JP S57176861A JP 56061176 A JP56061176 A JP 56061176A JP 6117681 A JP6117681 A JP 6117681A JP S57176861 A JPS57176861 A JP S57176861A
Authority
JP
Japan
Prior art keywords
terminal equipment
buffer memory
buffer
overflows
overflow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56061176A
Other languages
Japanese (ja)
Other versions
JPH0217978B2 (en
Inventor
Isao Yoshino
Toyokazu Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56061176A priority Critical patent/JPS57176861A/en
Publication of JPS57176861A publication Critical patent/JPS57176861A/en
Publication of JPH0217978B2 publication Critical patent/JPH0217978B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Small-Scale Networks (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer And Data Communications (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To quickly send negative acknowledgements to the transmitting station, by independently providing a buffer memory and its overflow detecting means corresponding to each terminal equipment and by reporting reception- impossible condition of corresponding terminal equipment when the memory overflows. CONSTITUTION:Terminal equipment 100 has buffer memories 121-12n for buffering transmitted and received data, which are independently installed corresponding to terminal equipment, and overflow detecting circuits 141-14n of each buffer memory. When any one of the buffer memories 121-12n overflows at the time of data reception, an overflow message regarding the terminal equipment 210-21n corresponding to the buffer memory 121-12n is transmitted to the transmitting station.
JP56061176A 1981-04-24 1981-04-24 Terminal equipment Granted JPS57176861A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56061176A JPS57176861A (en) 1981-04-24 1981-04-24 Terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56061176A JPS57176861A (en) 1981-04-24 1981-04-24 Terminal equipment

Publications (2)

Publication Number Publication Date
JPS57176861A true JPS57176861A (en) 1982-10-30
JPH0217978B2 JPH0217978B2 (en) 1990-04-24

Family

ID=13163574

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56061176A Granted JPS57176861A (en) 1981-04-24 1981-04-24 Terminal equipment

Country Status (1)

Country Link
JP (1) JPS57176861A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228448A (en) * 1983-06-09 1984-12-21 Fujitsu Ltd Data reception control system
JPS60219891A (en) * 1984-03-26 1985-11-02 アルカテル・エヌ・ブイ Digital exchange system
JPS6130149A (en) * 1984-07-20 1986-02-12 Fujitsu Ltd Packet signal transfer system
JPS61191007U (en) * 1985-05-20 1986-11-28
JPS6380645A (en) * 1986-09-25 1988-04-11 Fuji Xerox Co Ltd Storage type star communication network
JPS6422139A (en) * 1987-07-17 1989-01-25 Fuji Electric Co Ltd Method for protecting data of broadcasting transmission system
JPH0191552A (en) * 1987-10-02 1989-04-11 Hitachi Ltd Data transmission equipment
JPH0295046A (en) * 1988-09-30 1990-04-05 Nippon Telegr & Teleph Corp <Ntt> Information repeating closing system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5482102A (en) * 1977-12-14 1979-06-30 Fujitsu Ltd Data communication system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5482102A (en) * 1977-12-14 1979-06-30 Fujitsu Ltd Data communication system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59228448A (en) * 1983-06-09 1984-12-21 Fujitsu Ltd Data reception control system
JPS60219891A (en) * 1984-03-26 1985-11-02 アルカテル・エヌ・ブイ Digital exchange system
JPH0476280B2 (en) * 1984-03-26 1992-12-03 Alcatel Nv
JPS6130149A (en) * 1984-07-20 1986-02-12 Fujitsu Ltd Packet signal transfer system
JPS61191007U (en) * 1985-05-20 1986-11-28
JPS6380645A (en) * 1986-09-25 1988-04-11 Fuji Xerox Co Ltd Storage type star communication network
JPS6422139A (en) * 1987-07-17 1989-01-25 Fuji Electric Co Ltd Method for protecting data of broadcasting transmission system
JPH0191552A (en) * 1987-10-02 1989-04-11 Hitachi Ltd Data transmission equipment
JPH0295046A (en) * 1988-09-30 1990-04-05 Nippon Telegr & Teleph Corp <Ntt> Information repeating closing system

Also Published As

Publication number Publication date
JPH0217978B2 (en) 1990-04-24

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