JPS5610955A - Semiconductor memory - Google Patents

Semiconductor memory

Info

Publication number
JPS5610955A
JPS5610955A JP8716579A JP8716579A JPS5610955A JP S5610955 A JPS5610955 A JP S5610955A JP 8716579 A JP8716579 A JP 8716579A JP 8716579 A JP8716579 A JP 8716579A JP S5610955 A JPS5610955 A JP S5610955A
Authority
JP
Japan
Prior art keywords
memory cell
minority carrier
channel
substrate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8716579A
Other languages
Japanese (ja)
Inventor
Masumi Nakao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8716579A priority Critical patent/JPS5610955A/en
Publication of JPS5610955A publication Critical patent/JPS5610955A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components

Abstract

PURPOSE:To contrive the extension of a memory retaining time of a semiconductor memory by forming a reverse conducting type diffused layer to a substrate between a memory cell and a carrier discharge source and applying prescribed constant voltage thereto to absorb minority carrier to the layer. CONSTITUTION:A reverse polarity diffused layer 3 to a substrate is disposed between a memory cell 1 and a bootstrap circuit 2.The circuit 2 is an electron minority carrier discharge source in an N-channel and a hole minority carrier discharge source in a P-channel.The layer 3 is connected at the positions 5 to wiring layers 4, and a power supply voltage VDD is applied thereto. A constant voltage higher than the substrate is applied when the memory cell is N-channel, while the constant voltage lower than the substrate is applied when the memory cell is P-channel. Since the layer 3 absorbes the minority carrier to reduce the minority carrier reaching the memory cell 1 from the circuit 2 according to this configuration, it can extend the memory retaining time. It can also shorten the distance between the cell 1 and the source 2 so as to reduce the size thereof.
JP8716579A 1979-07-09 1979-07-09 Semiconductor memory Pending JPS5610955A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8716579A JPS5610955A (en) 1979-07-09 1979-07-09 Semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8716579A JPS5610955A (en) 1979-07-09 1979-07-09 Semiconductor memory

Publications (1)

Publication Number Publication Date
JPS5610955A true JPS5610955A (en) 1981-02-03

Family

ID=13907368

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8716579A Pending JPS5610955A (en) 1979-07-09 1979-07-09 Semiconductor memory

Country Status (1)

Country Link
JP (1) JPS5610955A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198772A (en) * 1984-03-22 1985-10-08 Nec Ic Microcomput Syst Ltd Semiconductor integrated device
JPH01231539A (en) * 1988-03-11 1989-09-14 Hitachi Ltd Multi-point terminal system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068483A (en) * 1973-10-19 1975-06-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5068483A (en) * 1973-10-19 1975-06-07

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60198772A (en) * 1984-03-22 1985-10-08 Nec Ic Microcomput Syst Ltd Semiconductor integrated device
JPH01231539A (en) * 1988-03-11 1989-09-14 Hitachi Ltd Multi-point terminal system
JPH0683219B2 (en) * 1988-03-11 1994-10-19 株式会社日立製作所 Multipoint terminal system

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