JPS56108240A - Sorting method for semiconductor chip - Google Patents

Sorting method for semiconductor chip

Info

Publication number
JPS56108240A
JPS56108240A JP1054080A JP1054080A JPS56108240A JP S56108240 A JPS56108240 A JP S56108240A JP 1054080 A JP1054080 A JP 1054080A JP 1054080 A JP1054080 A JP 1054080A JP S56108240 A JPS56108240 A JP S56108240A
Authority
JP
Japan
Prior art keywords
chips
coated
resin layer
defective
sorting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1054080A
Other languages
Japanese (ja)
Inventor
Toshio Okubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP1054080A priority Critical patent/JPS56108240A/en
Publication of JPS56108240A publication Critical patent/JPS56108240A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67271—Sorting devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To provide a sorting method for semiconductor chips wherein the outer circumferential side surface of a semiconductor wafer is coated with a resin layer containing iron powder, the wafer is divided into chips and defective chips on the periphery are attracted by a magnet in order to separate and sort. CONSTITUTION:A plurality of wafers 1 are piled and bonded to form a unit 2, whose outer side surface is coated with a resin layer 3 containing a large quantity of iron powder, and the resin layer is hardened. The unit is divided into small segments each having a square cross-section to obtain good chips 4 and defective chips 4'. Because the chips 4' defective in shape are inevitably coated with the resin containing ion powder, they can be readily separated and sorted by a magnet 5.
JP1054080A 1980-01-31 1980-01-31 Sorting method for semiconductor chip Pending JPS56108240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1054080A JPS56108240A (en) 1980-01-31 1980-01-31 Sorting method for semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1054080A JPS56108240A (en) 1980-01-31 1980-01-31 Sorting method for semiconductor chip

Publications (1)

Publication Number Publication Date
JPS56108240A true JPS56108240A (en) 1981-08-27

Family

ID=11753083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1054080A Pending JPS56108240A (en) 1980-01-31 1980-01-31 Sorting method for semiconductor chip

Country Status (1)

Country Link
JP (1) JPS56108240A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140535U (en) * 1985-02-20 1986-08-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61140535U (en) * 1985-02-20 1986-08-30

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