JPS56108148A - Interface connection control system for program controller - Google Patents
Interface connection control system for program controllerInfo
- Publication number
- JPS56108148A JPS56108148A JP1087780A JP1087780A JPS56108148A JP S56108148 A JPS56108148 A JP S56108148A JP 1087780 A JP1087780 A JP 1087780A JP 1087780 A JP1087780 A JP 1087780A JP S56108148 A JPS56108148 A JP S56108148A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- interface
- microcommand
- normal
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To secure a use of an interface provided for the normal action even for the actions other than the normal action, by providing guard function of an internal interface to the microcommand itself. CONSTITUTION:The microcommand decoding circuit 40 decodes the access request given from the microcommand register 20 and puts the signal on the signal line 400-1. In this case, the normal state, the faulty state and the diagnosis state are divided to the signal lines 300-1-300-n to deliver the output according to either one of these states. On the other hand, either one of the designation signals of the external interface effectuating bit groups such as the bits 200-1-200-n which are affectuated in the normal, faulty and diagnosis states each is received, and thus the effective conditions of the interface are satisfied by the corresponding one of the AND circuit 50-1-50-n. The condition signal is obtained through the signal line 600 and via the OR circuit 60 in the form of the external access request signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1087780A JPS56108148A (en) | 1980-02-01 | 1980-02-01 | Interface connection control system for program controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1087780A JPS56108148A (en) | 1980-02-01 | 1980-02-01 | Interface connection control system for program controller |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56108148A true JPS56108148A (en) | 1981-08-27 |
JPS6161146B2 JPS6161146B2 (en) | 1986-12-24 |
Family
ID=11762552
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1087780A Granted JPS56108148A (en) | 1980-02-01 | 1980-02-01 | Interface connection control system for program controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56108148A (en) |
-
1980
- 1980-02-01 JP JP1087780A patent/JPS56108148A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6161146B2 (en) | 1986-12-24 |
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