FR2412107A1 - Programmed logic system - has logic control circuit decoding data signals from program memory - Google Patents

Programmed logic system - has logic control circuit decoding data signals from program memory

Info

Publication number
FR2412107A1
FR2412107A1 FR7738920A FR7738920A FR2412107A1 FR 2412107 A1 FR2412107 A1 FR 2412107A1 FR 7738920 A FR7738920 A FR 7738920A FR 7738920 A FR7738920 A FR 7738920A FR 2412107 A1 FR2412107 A1 FR 2412107A1
Authority
FR
France
Prior art keywords
data signals
control circuit
program memory
logic control
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7738920A
Other languages
French (fr)
Other versions
FR2412107B3 (en
Inventor
Louis Boudillon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Option NV
Original Assignee
Option NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Option NV filed Critical Option NV
Priority to FR7738920A priority Critical patent/FR2412107A1/en
Publication of FR2412107A1 publication Critical patent/FR2412107A1/en
Application granted granted Critical
Publication of FR2412107B3 publication Critical patent/FR2412107B3/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638—Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip

Abstract

The programmed logic system includes a processor and a programmed memory. The logic system includes a logic control circuit which receives data signals provided by the program memory at the request of the processor, and decodes them to provide new data signals. A multiplexer sends to the processor, either the data signals from the program memory, or the new data signals from the logic control circuit, following receipt of instructions from the logic control circuit.
FR7738920A 1977-12-16 1977-12-16 Programmed logic system - has logic control circuit decoding data signals from program memory Granted FR2412107A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7738920A FR2412107A1 (en) 1977-12-16 1977-12-16 Programmed logic system - has logic control circuit decoding data signals from program memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7738920A FR2412107A1 (en) 1977-12-16 1977-12-16 Programmed logic system - has logic control circuit decoding data signals from program memory

Publications (2)

Publication Number Publication Date
FR2412107A1 true FR2412107A1 (en) 1979-07-13
FR2412107B3 FR2412107B3 (en) 1980-09-12

Family

ID=9199247

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7738920A Granted FR2412107A1 (en) 1977-12-16 1977-12-16 Programmed logic system - has logic control circuit decoding data signals from program memory

Country Status (1)

Country Link
FR (1) FR2412107A1 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0017585A1 (en) * 1979-04-06 1980-10-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Method and system for operating an addressable memory allowing for the association at will of extensions contained in the memory
EP0017584A1 (en) * 1979-04-06 1980-10-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Method and system for operating an addressable memory allowing for the qualitative association at will with data contained in the memory
EP0017586A1 (en) * 1979-04-06 1980-10-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Data processing apparatus comprising two direct access memories cooperating as well in a reading as in a writing mode

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0017585A1 (en) * 1979-04-06 1980-10-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Method and system for operating an addressable memory allowing for the association at will of extensions contained in the memory
EP0017584A1 (en) * 1979-04-06 1980-10-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Method and system for operating an addressable memory allowing for the qualitative association at will with data contained in the memory
EP0017586A1 (en) * 1979-04-06 1980-10-15 COMPAGNIE INTERNATIONALE POUR L'INFORMATIQUE CII - HONEYWELL BULL (dite CII-HB) Data processing apparatus comprising two direct access memories cooperating as well in a reading as in a writing mode
FR2453467A1 (en) * 1979-04-06 1980-10-31 Cii Honeywell Bull METHOD AND SYSTEM FOR OPERATING AN ADDRESSABLE MEMORY FOR ASSOCIATING EXTENSIONS WITH THE DATA CONTAINED IN THE MEMORY
FR2453449A1 (en) * 1979-04-06 1980-10-31 Cii Honeywell Bull METHOD AND SYSTEM FOR OPERATING AN ADDRESSABLE MEMORY FOR IDENTIFYING CERTAIN PARTICULAR ADDRESSES
FR2453468A1 (en) * 1979-04-06 1980-10-31 Cii Honeywell Bull METHOD AND SYSTEM FOR OPERATING AN ADDRESSABLE MEMORY ALLOWING TO ASSOCIATE QUALIFIERS WITH THE DATA CONTAINED IN THE MEMORY

Also Published As

Publication number Publication date
FR2412107B3 (en) 1980-09-12

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