JPS56105544A - System fault analyzing system - Google Patents
System fault analyzing systemInfo
- Publication number
- JPS56105544A JPS56105544A JP858480A JP858480A JPS56105544A JP S56105544 A JPS56105544 A JP S56105544A JP 858480 A JP858480 A JP 858480A JP 858480 A JP858480 A JP 858480A JP S56105544 A JPS56105544 A JP S56105544A
- Authority
- JP
- Japan
- Prior art keywords
- information
- physical addresses
- addresses
- address
- disc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE:To make the detection of faults easy by storing the logic addresses and physical addresses of a random-accessible memory means in pairs into an address conversion means and reading out the storage contents assigned by the physical addresses. CONSTITUTION:The contents of a magnetic tape 1 having recorded all of memory information are transferred by a transfer mechanism 6 to a magnetic disc 7. At this time, the physical addresses of the disc 7 and the physical address information at the making of the tape 1 are stored in pairs from the mechanism 6 into a mapping mechanism 8. The top address and state information of the 1st block have beforehand been stored in a random address mechanism 9, and the logic addresses are applied from the mechanism 9 to the mechanism 8. The corresponding physical addresses are applied to the disc 7. The contents of the positions assigned by the physical addresses are applied to the mechanism 9, and these pieces of information of the mechanism 9 are applied in a set to a control block reproducing mechanism 10. The mechanism 10 edits such information in an easy-to-fault-analyze manner, after which said information is printed with a printer 2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP858480A JPS56105544A (en) | 1980-01-28 | 1980-01-28 | System fault analyzing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP858480A JPS56105544A (en) | 1980-01-28 | 1980-01-28 | System fault analyzing system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56105544A true JPS56105544A (en) | 1981-08-22 |
JPS6141424B2 JPS6141424B2 (en) | 1986-09-16 |
Family
ID=11697048
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP858480A Granted JPS56105544A (en) | 1980-01-28 | 1980-01-28 | System fault analyzing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56105544A (en) |
-
1980
- 1980-01-28 JP JP858480A patent/JPS56105544A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6141424B2 (en) | 1986-09-16 |
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