JPS56101691A - Refresh control system - Google Patents

Refresh control system

Info

Publication number
JPS56101691A
JPS56101691A JP286980A JP286980A JPS56101691A JP S56101691 A JPS56101691 A JP S56101691A JP 286980 A JP286980 A JP 286980A JP 286980 A JP286980 A JP 286980A JP S56101691 A JPS56101691 A JP S56101691A
Authority
JP
Japan
Prior art keywords
memory
cpu3
circuit
output
refresh control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP286980A
Other languages
Japanese (ja)
Inventor
Takashi Hiraoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP286980A priority Critical patent/JPS56101691A/en
Publication of JPS56101691A publication Critical patent/JPS56101691A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)

Abstract

PURPOSE:To reduce the electric power consumption of backup operation by exercising memory control with the output of a basic power circuit normally and by permitting to perform refresh control by itself when the power source is abnormal. CONSTITUTION:While basic power circuit 1 is in normal operation, its output DC voltage is supplied to CPU3 and nonvolatile memory 4 to put the system in normal operation, and the memory is refreshed through CPU3. If the supply of commercial AC power source 2 is excluded or if the output is excluded owing to a fault of circuit 1, switching device 5 supplies the output of battery 6 to memory 4. Consequently, the memory contents of memory 4 are retained. Then, CPU3 monitors the operation state of circuit 1 invariably and, if a failure occurs, sends a refresh start signal from a refresh oscillator to a refresh control circuit, from which a refresh control signal is outputted to a memory element. Thus, the memory exercises refresh control by itself, and consequently the need to back up the power source of CPU3, so that the power consumption of the backup operation can be reduced.
JP286980A 1980-01-14 1980-01-14 Refresh control system Pending JPS56101691A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP286980A JPS56101691A (en) 1980-01-14 1980-01-14 Refresh control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP286980A JPS56101691A (en) 1980-01-14 1980-01-14 Refresh control system

Publications (1)

Publication Number Publication Date
JPS56101691A true JPS56101691A (en) 1981-08-14

Family

ID=11541356

Family Applications (1)

Application Number Title Priority Date Filing Date
JP286980A Pending JPS56101691A (en) 1980-01-14 1980-01-14 Refresh control system

Country Status (1)

Country Link
JP (1) JPS56101691A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001095335A1 (en) * 2000-06-08 2001-12-13 Mitsubishi Denki Kabushiki Kaisha Data backup device and step-up/step-down power supply
CN106816180A (en) * 2015-11-27 2017-06-09 爱思开海力士有限公司 Memory device and its operating method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001095335A1 (en) * 2000-06-08 2001-12-13 Mitsubishi Denki Kabushiki Kaisha Data backup device and step-up/step-down power supply
CN106816180A (en) * 2015-11-27 2017-06-09 爱思开海力士有限公司 Memory device and its operating method
CN106816180B (en) * 2015-11-27 2020-11-10 爱思开海力士有限公司 Memory device and method of operating the same

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