JPS5599746A - Method for construction of multi-layer wiring - Google Patents

Method for construction of multi-layer wiring

Info

Publication number
JPS5599746A
JPS5599746A JP749779A JP749779A JPS5599746A JP S5599746 A JPS5599746 A JP S5599746A JP 749779 A JP749779 A JP 749779A JP 749779 A JP749779 A JP 749779A JP S5599746 A JPS5599746 A JP S5599746A
Authority
JP
Japan
Prior art keywords
film
layer
layer wiring
evaporated
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP749779A
Other languages
Japanese (ja)
Inventor
Ryuichiro Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP749779A priority Critical patent/JPS5599746A/en
Publication of JPS5599746A publication Critical patent/JPS5599746A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To secure good contact between the 1st and the 2nd layer wirings by the manufacturing process similar to the conventional one by a method wherein thin Ti film layer is continuously evaporated on an Al film in forming Al film and thin Ti film, which are to become a gate metal and the 1st layer wiring metal. CONSTITUTION:Active layer 12 is provided on semiinsulating GaAs substrate 11, and Al film 13 is continuously evaporated to a thickness of 4000Angstrom , and Ti film 18 to a thickness of about 100-150Angstrom . Next, in the same way as in the conventional process, gate electrode 13a and the 1st layer wiring 13b are formed simultaneously, and then an ohmic electrode is formed. Further, by the CVD method, SiO2 insulating film 15 is piled up, and contact hole 16 is formed. Subsequently, the 2nd layer wiring metal 17 consisting of Cr/Pt/Au is evaporated, and the desired wiring pattern is formed.
JP749779A 1979-01-24 1979-01-24 Method for construction of multi-layer wiring Pending JPS5599746A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP749779A JPS5599746A (en) 1979-01-24 1979-01-24 Method for construction of multi-layer wiring

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP749779A JPS5599746A (en) 1979-01-24 1979-01-24 Method for construction of multi-layer wiring

Publications (1)

Publication Number Publication Date
JPS5599746A true JPS5599746A (en) 1980-07-30

Family

ID=11667404

Family Applications (1)

Application Number Title Priority Date Filing Date
JP749779A Pending JPS5599746A (en) 1979-01-24 1979-01-24 Method for construction of multi-layer wiring

Country Status (1)

Country Link
JP (1) JPS5599746A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8594242B2 (en) 2001-11-13 2013-11-26 Panasonic Corporation Method of receiving modulation symbols

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944797A (en) * 1972-06-19 1974-04-27
JPS51147286A (en) * 1975-06-13 1976-12-17 Nec Corp Manufacturing process of semiconductor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4944797A (en) * 1972-06-19 1974-04-27
JPS51147286A (en) * 1975-06-13 1976-12-17 Nec Corp Manufacturing process of semiconductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8594242B2 (en) 2001-11-13 2013-11-26 Panasonic Corporation Method of receiving modulation symbols

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