JPS5599624A - Storing system for error informatiom - Google Patents

Storing system for error informatiom

Info

Publication number
JPS5599624A
JPS5599624A JP617579A JP617579A JPS5599624A JP S5599624 A JPS5599624 A JP S5599624A JP 617579 A JP617579 A JP 617579A JP 617579 A JP617579 A JP 617579A JP S5599624 A JPS5599624 A JP S5599624A
Authority
JP
Japan
Prior art keywords
memory
error
microorder
signal
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP617579A
Other languages
Japanese (ja)
Inventor
Hiroo Fujisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP617579A priority Critical patent/JPS5599624A/en
Publication of JPS5599624A publication Critical patent/JPS5599624A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To realize omission of the intermediate buffer which memorizes the memory error, by giving the discontinuation to the microorder and then storing the memory error information into the work memory in case the memory access error is detected at the memory request control part.
CONSTITUTION: In case the error relating the memory access is detected at the memory request control part, both the stop and end signals are transmitted to the microorder control part. The microorder control part resets the reading register of the control memory via the stop signal to prevent the output of writing and reading indications WC and RC to be given to work memory WM1 by the microorder. Instead, writing signal 15 is delivered by the end signal, and memory access error detail information can be written into WM1. Input line 11 of the error information is selected to be the input of WM1 only in the latter half of the end signal, and signal 15 is delivered in the latter half of the end signal. In such way, the intermediate buffer can be omitted, thus decreasing the hardware quantity.
COPYRIGHT: (C)1980,JPO&Japio
JP617579A 1979-01-24 1979-01-24 Storing system for error informatiom Pending JPS5599624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP617579A JPS5599624A (en) 1979-01-24 1979-01-24 Storing system for error informatiom

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP617579A JPS5599624A (en) 1979-01-24 1979-01-24 Storing system for error informatiom

Publications (1)

Publication Number Publication Date
JPS5599624A true JPS5599624A (en) 1980-07-29

Family

ID=11631205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP617579A Pending JPS5599624A (en) 1979-01-24 1979-01-24 Storing system for error informatiom

Country Status (1)

Country Link
JP (1) JPS5599624A (en)

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