JPS5597764A - Decoding circuit for dmi code - Google Patents

Decoding circuit for dmi code

Info

Publication number
JPS5597764A
JPS5597764A JP514479A JP514479A JPS5597764A JP S5597764 A JPS5597764 A JP S5597764A JP 514479 A JP514479 A JP 514479A JP 514479 A JP514479 A JP 514479A JP S5597764 A JPS5597764 A JP S5597764A
Authority
JP
Japan
Prior art keywords
circuit
circuits
signal
integrating
systems
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP514479A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6337990B2 (enrdf_load_stackoverflow
Inventor
Toshikazu Matsumoto
Risuke Shimodaira
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP514479A priority Critical patent/JPS5597764A/ja
Publication of JPS5597764A publication Critical patent/JPS5597764A/ja
Publication of JPS6337990B2 publication Critical patent/JPS6337990B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
    • H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
    • H04L25/491—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes using 1B2B codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Dc Digital Transmission (AREA)
JP514479A 1979-01-19 1979-01-19 Decoding circuit for dmi code Granted JPS5597764A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP514479A JPS5597764A (en) 1979-01-19 1979-01-19 Decoding circuit for dmi code

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP514479A JPS5597764A (en) 1979-01-19 1979-01-19 Decoding circuit for dmi code

Publications (2)

Publication Number Publication Date
JPS5597764A true JPS5597764A (en) 1980-07-25
JPS6337990B2 JPS6337990B2 (enrdf_load_stackoverflow) 1988-07-27

Family

ID=11603098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP514479A Granted JPS5597764A (en) 1979-01-19 1979-01-19 Decoding circuit for dmi code

Country Status (1)

Country Link
JP (1) JPS5597764A (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952948A (ja) * 1982-09-20 1984-03-27 Nippon Telegr & Teleph Corp <Ntt> 符号伝送方式

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244108A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Code error detection equipment

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5244108A (en) * 1975-10-06 1977-04-06 Hitachi Ltd Code error detection equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952948A (ja) * 1982-09-20 1984-03-27 Nippon Telegr & Teleph Corp <Ntt> 符号伝送方式

Also Published As

Publication number Publication date
JPS6337990B2 (enrdf_load_stackoverflow) 1988-07-27

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