JPS5587393A - Memory device possessing memory initializing function - Google Patents

Memory device possessing memory initializing function

Info

Publication number
JPS5587393A
JPS5587393A JP15900878A JP15900878A JPS5587393A JP S5587393 A JPS5587393 A JP S5587393A JP 15900878 A JP15900878 A JP 15900878A JP 15900878 A JP15900878 A JP 15900878A JP S5587393 A JPS5587393 A JP S5587393A
Authority
JP
Japan
Prior art keywords
memory
circuit
reading
autonomous
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15900878A
Other languages
Japanese (ja)
Inventor
Haruhiko Tsunoda
Shigeki Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15900878A priority Critical patent/JPS5587393A/en
Publication of JPS5587393A publication Critical patent/JPS5587393A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To prevent occurrence of the undesired error at the moment when the reading access is given by generating the incorporation enable signal after carrying out the autonomous initial resetting and the reading check at the side of the memory device.
CONSTITUTION: The power source ON is informed from control part 17-0 to memory access control part 13-0 via the ON of power input signal POW, and as a result an autonomous starting is given to read/write access circuit 6-0 to perform the initial setting of memory unit 5. After this, part 13-0 gives an autonomous starting again to circuit 6-0, and then unit 5-0 perform reading in the order of the addresses. At the same time, error check circuit 7-0 generates the syndrome to carry out the error detection and correction for each reading data. And then the structure control register is set, and the incorporation enable signal is supplied to the memory control unit from AND circuit 21-0.
COPYRIGHT: (C)1980,JPO&Japio
JP15900878A 1978-12-22 1978-12-22 Memory device possessing memory initializing function Pending JPS5587393A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15900878A JPS5587393A (en) 1978-12-22 1978-12-22 Memory device possessing memory initializing function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15900878A JPS5587393A (en) 1978-12-22 1978-12-22 Memory device possessing memory initializing function

Publications (1)

Publication Number Publication Date
JPS5587393A true JPS5587393A (en) 1980-07-02

Family

ID=15684218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15900878A Pending JPS5587393A (en) 1978-12-22 1978-12-22 Memory device possessing memory initializing function

Country Status (1)

Country Link
JP (1) JPS5587393A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024658A (en) * 1983-07-19 1985-02-07 Fujitsu Ltd Initializing method of buffer memory

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6024658A (en) * 1983-07-19 1985-02-07 Fujitsu Ltd Initializing method of buffer memory
JPH0430623B2 (en) * 1983-07-19 1992-05-22

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