JPS5583339A - Signal converter circuit - Google Patents
Signal converter circuitInfo
- Publication number
- JPS5583339A JPS5583339A JP15644078A JP15644078A JPS5583339A JP S5583339 A JPS5583339 A JP S5583339A JP 15644078 A JP15644078 A JP 15644078A JP 15644078 A JP15644078 A JP 15644078A JP S5583339 A JPS5583339 A JP S5583339A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- elements
- state
- computer
- false input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To make a fault diagnosis possible in a system operation state by generating a false input signal under no influence of the contact state of a plant, by internally providing a false input setting signal generating circuit. CONSTITUTION:Switch element 1a is turned OFF by check start signal 20. On the other hand, false input setting signal 19 from a computer is set to a logical signal level ''Low'' and switch elements 8 and 9 are turned OFF and ON respectively via gate elements 11-13. In this state, input voltage ei at an input signal reception terminal is OV regardless of states of contacts 3a-3n of a plant. Consequently, comparator circuits 1a-1n operate and gate elements 2a-2n output logical signal ''1'' to the computer. To perform operation equivalent to the turning-OFF of contacts 3a-3n, on the contrary, logic level ''HIGH'' is set to false input setting signal 19 from the computer. In this state elements 8 and 9 are ON and OFF respectively and voltage ei is +VB. Consequently, none of circuits 1a-1n operates and elements 2a-2n output signal 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15644078A JPS5583339A (en) | 1978-12-20 | 1978-12-20 | Signal converter circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15644078A JPS5583339A (en) | 1978-12-20 | 1978-12-20 | Signal converter circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5583339A true JPS5583339A (en) | 1980-06-23 |
Family
ID=15627791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15644078A Pending JPS5583339A (en) | 1978-12-20 | 1978-12-20 | Signal converter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5583339A (en) |
-
1978
- 1978-12-20 JP JP15644078A patent/JPS5583339A/en active Pending
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