JP2867504B2 - Output buffer circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit such as a digital IC.

[Conventional technology]

Conventionally, this type of output buffer circuit has a P-type MOS transistor on the high level supply side and an N-type MOS transistor on the low level supply side.
It was composed of an inverter with transistors and was manufactured and classified into CMOS output level and TTL output level specifications according to the application.

[Problems to be solved by the invention]

The above-described conventional output buffer circuit includes P-type and N-type output buffer circuits.
Because it is composed of inverters with MOS transistors, in the function test, especially in the type that supplies CMOS output levels, if there is a continuous level switching operation of multiple outputs, the output amplitude is large,
There has been a drawback that the power supply line and the ground line fluctuate greatly due to charging and discharging of the additional capacitance of the output terminal, and a malfunction is likely to occur.

An object of the present invention is to provide an output buffer circuit capable of performing a function test stably without malfunction.

[Means for solving the problem]

The output buffer circuit according to the present invention outputs a first signal having a level corresponding to the level of the input signal when the switching control signal is at the first and second levels, and outputs the first signal when the switching control signal is at the first level. A second signal which becomes the same level as the signal No. 1 and becomes an inactive level when it is at the second level, and becomes inactive when the switching control signal is at the first level.
And a control circuit for outputting a third signal having a level obtained by inverting the first signal at the level of the first signal, and connecting the source to the first power supply terminal and connecting the drain to the output terminal to output the first signal. One conductivity type first MOS that is turned on / off by
A transistor and a source are connected to a second power supply terminal, and a drain is connected to the output terminal. When the switching control signal is at a first level, the switching control signal is turned on / off by the second signal to turn on and off at a second level. An inverter provided with a second MOS transistor of a reverse conductivity type that is turned off by the second signal, and a source connected to the output terminal and a drain connected to the second power supply terminal. The signal is first
Is turned off by the third signal,
And a third MOS transistor of one conductivity type which is turned on / off by the third signal when the level is at the level of.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment includes an inverter I ₁ and the gate circuit G _1, G _2, the switching control signal SWC outputs a first signal V ₁ of the low and high same level as the level of the input signal IN when the , When the switching control signal SWC is at a low level, the first signal V ₁
The same level as the second and the high level when the level is high
Outputs of patience V _2, the control circuit 1 switching control signal SWC to output a third signal V ₃ to a low level low level and the high level inverted level of the first signal V ₁ when the time, the first MOS transistor MT ₁ of N-type which is turned on and off in response to the first signal V ₁ and connecting the drain to the output terminal T ₀ is connected to the ground terminal of the source the first power supply terminal, and a source first is when the second power supply terminal (power supply voltage V _CC) and connected to the switch control signal SWC connects the drain to the output terminal T ₀ is low when the high-level to turn on and off by the second signal V ₂ an inverter 2 having a second MOS transistor MT ₂ P-type as the second off by the signal V _2, the output of the source terminal T
₀ and the drain is connected to the second power supply terminal (V _CC ). When the switching control signal SWC is at a low level, the third signal V ₃
Has a configuration and a third MOS transistor MT ₃ of N-type which is turned on and off in response to the third signal V ₃ is at high level turns off the.

With such a configuration, the switching control signal SWC
During normal operation at a low level, the third MOS transistor MT ₃
Is turned off, and the inverter 2 outputs the normal logical amplitude output signal OUT.

Moreover, switching to the time control signal SWC is high von transfection test, the second MOS transistor MT ₂ is turned off, the first MOS transistor MT ₁ and the third transistor
MT ₃ and inverter is constituted by, in this case, only the third gate-source voltage of the transistor MT ₃ in the output signal O
Since the logical amplitude of the UT is reduced, it is possible to reduce the level of charge and discharge caused by additional capacitance of the output terminal T _0, it is possible to prevent the occurrence of malfunction.

 FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, a function is added to set the output to a high impedance state when the input control signal IOC is at a low level. The level of the input signal IN and the level of the output signal OUT are non-inverted. In addition, the basic operation is the first
This is the same as the embodiment.

〔The invention's effect〕

As described above, the present invention relates to the second MO of the CMOS inverter formed by the first and second MOS transistors.
A third MOS transistor of the same conductivity type as the first MOS transistor is provided in parallel with the S transistor. During normal operation, the third MOS transistor is turned off and the first and second MOS transistors are turned off.
An inverter is formed by transistors, and the second MOS transistor is turned off during the function test and the inverter is formed by the first and third MOS transistors. Since the size can be reduced by the MOS transistor, the level of charge / discharge due to the additional capacitance of the output terminal can be reduced, so that there is an effect that malfunction can be prevented and a function test can be stably performed.

[Brief description of the drawings]

FIG. 1 and FIG. 2 are circuit diagrams showing first and second embodiments of the present invention, respectively. 1, 1 _A ...... control circuit, 2 ...... inverter, G ₁ ~G ₆ ...... gate circuit, I _1, I ₂ ...... inverter, MT ₁ to MT ₃ ...... MOS transistor.

Claims (1)

(57) [Claims] 1. A first signal having a level corresponding to the level of an input signal is output when the switching control signal is at a first and second level, and a first signal is output when the switching control signal is at a first level. And outputs a second signal which becomes the inactive level when the switching control signal is at the first level and becomes inactive when the switching control signal is at the second level. A control circuit for outputting a third signal having an inverted level; a first conductive type of connecting a source to a first power supply terminal, connecting a drain to an output terminal, and turning on / off by the first signal; One MOS transistor and a source are connected to a second power supply terminal and a drain is connected to the output terminal. When the switching control signal is at a first level, the switching control signal is turned on / off by the second signal and the second control signal is turned on and off. At the level of the second signal The second MO opposite conductivity type which becomes Riofu
An inverter having an S transistor; a source connected to the output terminal; a drain connected to the second power supply terminal; and when the switching control signal is at the first level, the switching is turned off by the third signal. An output buffer circuit having a one-conductivity-type third MOS transistor which is turned on / off by the third signal when the level is 2.