JPS5583257A - Fabricating method of semiconductor device - Google Patents

Fabricating method of semiconductor device

Info

Publication number
JPS5583257A
JPS5583257A JP15631278A JP15631278A JPS5583257A JP S5583257 A JPS5583257 A JP S5583257A JP 15631278 A JP15631278 A JP 15631278A JP 15631278 A JP15631278 A JP 15631278A JP S5583257 A JPS5583257 A JP S5583257A
Authority
JP
Japan
Prior art keywords
layer
resistor
film
electrode
perforated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15631278A
Other languages
Japanese (ja)
Inventor
Hisakazu Iizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15631278A priority Critical patent/JPS5583257A/en
Publication of JPS5583257A publication Critical patent/JPS5583257A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout

Abstract

PURPOSE:To provide a resistor having high resistance such as approx. 10<5>MOMEGA adapted for a large capacity memory by forming polycrystalline silicon layer on a semiconductor substrate, using it for one electrode, and anodizing it to convert part of the polycrystalline silicon layer into the resistor. CONSTITUTION:A thick field oxide film 22 and a thin gate oxide film 23 enclosed by the film 22 are formed on a p-type silicon substrate 21, an opening is perforated at the end of the film 23, a polycrystalline silicon layer 24 is accumulated on the entire surface thereof, and an n<+>-type impurity is diffused therein to thereby form conductive region. Then, the layer 24 is patterned to be retained as a gate electrode 25 and to be also retained in a resistor forming region, and opening is perforated in the film 23 with the electrode 25 as a mask, and n-type source and drain regions 26 and 27 are thus formed in the substrate 21. Then, the entire surface is coated by a Si3N4 film 28, an opening is perforated in a resistor forming region, the layer 24 is exposed, an anodization is conducted with the layer 24 as one electrode, and the exposed portion is altered to SiOx as a resistor 29. Thereafter, the film 28 is removed, the layer 24 is patterned, and an electrode 29' is mounted on the layer 24 connected to the resistor 29.
JP15631278A 1978-12-20 1978-12-20 Fabricating method of semiconductor device Pending JPS5583257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15631278A JPS5583257A (en) 1978-12-20 1978-12-20 Fabricating method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15631278A JPS5583257A (en) 1978-12-20 1978-12-20 Fabricating method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5583257A true JPS5583257A (en) 1980-06-23

Family

ID=15625039

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15631278A Pending JPS5583257A (en) 1978-12-20 1978-12-20 Fabricating method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5583257A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046491A (en) * 1996-02-19 2000-04-04 Nec Corporation Semiconductor resistor element having improved resistance tolerance and semiconductor device therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6046491A (en) * 1996-02-19 2000-04-04 Nec Corporation Semiconductor resistor element having improved resistance tolerance and semiconductor device therefor

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