JPS5580336A - Manufacture of multi-layer wiring semiconductor device - Google Patents

Manufacture of multi-layer wiring semiconductor device

Info

Publication number
JPS5580336A
JPS5580336A JP15454078A JP15454078A JPS5580336A JP S5580336 A JPS5580336 A JP S5580336A JP 15454078 A JP15454078 A JP 15454078A JP 15454078 A JP15454078 A JP 15454078A JP S5580336 A JPS5580336 A JP S5580336A
Authority
JP
Japan
Prior art keywords
film
mask
exposed
converted
manufacture
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15454078A
Other languages
Japanese (ja)
Inventor
Masaru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15454078A priority Critical patent/JPS5580336A/en
Publication of JPS5580336A publication Critical patent/JPS5580336A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To eliminate excess of etching in the direction of depth by the method such that when Al wiring provided on a semiconductor substrate is separated, anode-oxidization is operated by using a photoresist film and an Si3N4 film as mask, and interlines are converted into porous Al2O3 film.
CONSTITUTION: On Si substrate 1 composed of SiO2 film 2 and impurity diffusion region 3, a laminate of Al film 4, PtSi film 5 and Si3N4 film 6 is coated. Next, on top of this, photoresist film mask 7a having a wiring pattern is provided. Exposed film 6 and 5 are removed by plasma etching. Film 4 on the exposed end is anode- oxidized, and it is converted into porous Al2O3 film 8. Subsequently, mask 7a is converted into 7b, and in a similar manner, the exposed part of film 6 is removed; an by removing mask 7b, the entire surface is coated with SiO2 film and silica film 10, and then this is covered with mask 7c. Next, by using a window provided on mask 7c, film 5 is removed and then mask 7c and film 10 are removed. Then, a laminated wiring consisting of Ti film 12, Pt film 13 and Au film 14 is fitted on exposed film 4.
COPYRIGHT: (C)1980,JPO&Japio
JP15454078A 1978-12-12 1978-12-12 Manufacture of multi-layer wiring semiconductor device Pending JPS5580336A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15454078A JPS5580336A (en) 1978-12-12 1978-12-12 Manufacture of multi-layer wiring semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15454078A JPS5580336A (en) 1978-12-12 1978-12-12 Manufacture of multi-layer wiring semiconductor device

Publications (1)

Publication Number Publication Date
JPS5580336A true JPS5580336A (en) 1980-06-17

Family

ID=15586484

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15454078A Pending JPS5580336A (en) 1978-12-12 1978-12-12 Manufacture of multi-layer wiring semiconductor device

Country Status (1)

Country Link
JP (1) JPS5580336A (en)

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