JPS5558548A - Forming of wiring metal pattern of semiconductor device - Google Patents

Forming of wiring metal pattern of semiconductor device

Info

Publication number
JPS5558548A
JPS5558548A JP13120178A JP13120178A JPS5558548A JP S5558548 A JPS5558548 A JP S5558548A JP 13120178 A JP13120178 A JP 13120178A JP 13120178 A JP13120178 A JP 13120178A JP S5558548 A JPS5558548 A JP S5558548A
Authority
JP
Japan
Prior art keywords
layer
fitted
pattern
wiring
wiring metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13120178A
Other languages
Japanese (ja)
Inventor
Norio Suzuki
Yuji Kajiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP13120178A priority Critical patent/JPS5558548A/en
Publication of JPS5558548A publication Critical patent/JPS5558548A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE: To cut the connection between an electrode to be retained and a wiring layer to be removed and make it easy to form a pattern, by providing a gap between an upper layer and a lower layer by using a laminated mask when a metal wiring layer is formed on a semiconductor base plate via an insulating layer having a window.
CONSTITUTION: Insulating layer 7 is fitted to semiconductor base plate 1 on which semiconductor elements are formed. Window 8 is provided on the diffusion region, and platinum silicide layer 9 is fitted here. Next, the entire surface is fitted with photosensitive resin layer 10 Al film and 11, which cannot be corroded by plasma etching. By photoetching, only film 11 is made into pattern 11'. Subsequently, by using this as mask, layer 10 is plasma-etched. Layer 10 is pushed under pattern 11', and a canopy is formed for pattern 11'. Next, the entire surface is fitted with wiring metal layer 13 made of Ti, Pt, Au, and gap 14 is produced below the canopy, and thereby layer 13a fitted into layer 9 and layer 13b fitted on the surface are made to be cut easily. Subsequently, only layer 13a is retained and layer 13b is removed.
COPYRIGHT: (C)1980,JPO&Japio
JP13120178A 1978-10-25 1978-10-25 Forming of wiring metal pattern of semiconductor device Pending JPS5558548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13120178A JPS5558548A (en) 1978-10-25 1978-10-25 Forming of wiring metal pattern of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13120178A JPS5558548A (en) 1978-10-25 1978-10-25 Forming of wiring metal pattern of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5558548A true JPS5558548A (en) 1980-05-01

Family

ID=15052393

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13120178A Pending JPS5558548A (en) 1978-10-25 1978-10-25 Forming of wiring metal pattern of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5558548A (en)

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