JPS5574179A - Semiconductor non-volatile memory - Google Patents

Semiconductor non-volatile memory

Info

Publication number
JPS5574179A
JPS5574179A JP14648678A JP14648678A JPS5574179A JP S5574179 A JPS5574179 A JP S5574179A JP 14648678 A JP14648678 A JP 14648678A JP 14648678 A JP14648678 A JP 14648678A JP S5574179 A JPS5574179 A JP S5574179A
Authority
JP
Japan
Prior art keywords
layer
gate
word line
current
npn
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14648678A
Other languages
Japanese (ja)
Other versions
JPS5732512B2 (en
Inventor
Tomoyuki Watabe
Kenji Kaneko
Toru Nakamura
Yutaka Okada
Takahiro Okabe
Jiyou Nagata
Yokichi Ito
Tatsu Toriyabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14648678A priority Critical patent/JPS5574179A/en
Priority to US06/096,388 priority patent/US4429326A/en
Priority to GB7940890A priority patent/GB2037076B/en
Priority to DE2947920A priority patent/DE2947920C2/en
Priority to CA340,918A priority patent/CA1128660A/en
Priority to NL7908660A priority patent/NL7908660A/en
Publication of JPS5574179A publication Critical patent/JPS5574179A/en
Publication of JPS5732512B2 publication Critical patent/JPS5732512B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:To provide an I<2>L with non-volatile memory function by forming a p- type control layer close to the base layer of NPN-transistor of I<2>L and further providing a floating gate through an insulator film on the substrate surface between the both layers. CONSTITUTION:A floating gate 23 is provided through an insulator film 22 between the base layer 15 and the control layer 21 in an NPN-transistor. The layer 14 consisting of word line is p-type isolation layer and common with I<2>L in the direction of word line. When no electrons are present in the gate 23, it functions as normal I<2>L. The presence of electrons in the gate 23 allows channel to be formed in n-layer 25, holes to be flowed from p-layer 13 to p-layer 21, and the base current to reduce thereby reducing the collector 16 current. This allows the amount of electron accumulated in the gate 23 to be detected as the change in the collector current, enabling memory operation. To perform writing, pn-junction of the layers 21 and 14 are subject to breakdown to allow electron injection. For reading, designated word line is made to zero potential and other word lines to a high level. To erase the memory, ultraviolet ray is irradiated on the element.
JP14648678A 1978-11-29 1978-11-29 Semiconductor non-volatile memory Granted JPS5574179A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP14648678A JPS5574179A (en) 1978-11-29 1978-11-29 Semiconductor non-volatile memory
US06/096,388 US4429326A (en) 1978-11-29 1979-11-21 I2 L Memory with nonvolatile storage
GB7940890A GB2037076B (en) 1978-11-29 1979-11-27 Nonvolatile semiconductor memory
DE2947920A DE2947920C2 (en) 1978-11-29 1979-11-28 Component in I → 2 → L-circuit technology
CA340,918A CA1128660A (en) 1978-11-29 1979-11-29 Nonvolatile semiconductor memory
NL7908660A NL7908660A (en) 1978-11-29 1979-11-29 SEMICONDUCTOR MEMORY.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14648678A JPS5574179A (en) 1978-11-29 1978-11-29 Semiconductor non-volatile memory

Publications (2)

Publication Number Publication Date
JPS5574179A true JPS5574179A (en) 1980-06-04
JPS5732512B2 JPS5732512B2 (en) 1982-07-12

Family

ID=15408712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14648678A Granted JPS5574179A (en) 1978-11-29 1978-11-29 Semiconductor non-volatile memory

Country Status (1)

Country Link
JP (1) JPS5574179A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0449596A (en) * 1990-06-19 1992-02-18 Nec Corp Memory circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0449596A (en) * 1990-06-19 1992-02-18 Nec Corp Memory circuit

Also Published As

Publication number Publication date
JPS5732512B2 (en) 1982-07-12

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