JPS5574180A - Non-volatile memory - Google Patents

Non-volatile memory

Info

Publication number
JPS5574180A
JPS5574180A JP14648778A JP14648778A JPS5574180A JP S5574180 A JPS5574180 A JP S5574180A JP 14648778 A JP14648778 A JP 14648778A JP 14648778 A JP14648778 A JP 14648778A JP S5574180 A JPS5574180 A JP S5574180A
Authority
JP
Japan
Prior art keywords
layer
gate
transistor
layers
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14648778A
Other languages
Japanese (ja)
Other versions
JPS5732513B2 (en
Inventor
Tomoyuki Watabe
Kenji Kaneko
Toru Nakamura
Yutaka Okada
Takahiro Okabe
Jiyou Nagata
Yokichi Ito
Tatsu Toriyabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14648778A priority Critical patent/JPS5574180A/en
Priority to US06/096,388 priority patent/US4429326A/en
Priority to GB7940890A priority patent/GB2037076B/en
Priority to DE2947920A priority patent/DE2947920C2/en
Priority to NL7908660A priority patent/NL7908660A/en
Priority to CA340,918A priority patent/CA1128660A/en
Publication of JPS5574180A publication Critical patent/JPS5574180A/en
Publication of JPS5732513B2 publication Critical patent/JPS5732513B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Abstract

PURPOSE:To read out non-volatile memory by using accumulated charges within the floating gate to control carrier density present on the base surface of horizontal type pnp-transistor of an I<2>L. CONSTITUTION:n-Layer 22 on n<+>-layer 21 is formed with p-layers 23, 24, each covered with n<+>-layers 25, 26. A floating gate 28 is formed through an insulator film on the base of pnp-transistor of I<2>L consisting of the layers 24, 22, and 23. When no electrons are present in the gate 28, normal I<2>L function is performed. The presence of electrons in the gate 28 allows channel to be formed in the n-layer 22 under the gate thereby to increase the collector 25 current in the reverse npn- transistor. In this manner, the contents of memory can be read out by the changes in the collector current of npn-transistor. pn-Junction of word line (the layer 24) and bit line (the layer 26) undergoes breakdown to write in the gate. The desired word line is applied with voltage to produce bit line (the layer 25) current for reading. Ultraviolet radiation is used to erase the memory.
JP14648778A 1978-11-29 1978-11-29 Non-volatile memory Granted JPS5574180A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP14648778A JPS5574180A (en) 1978-11-29 1978-11-29 Non-volatile memory
US06/096,388 US4429326A (en) 1978-11-29 1979-11-21 I2 L Memory with nonvolatile storage
GB7940890A GB2037076B (en) 1978-11-29 1979-11-27 Nonvolatile semiconductor memory
DE2947920A DE2947920C2 (en) 1978-11-29 1979-11-28 Component in I → 2 → L-circuit technology
NL7908660A NL7908660A (en) 1978-11-29 1979-11-29 SEMICONDUCTOR MEMORY.
CA340,918A CA1128660A (en) 1978-11-29 1979-11-29 Nonvolatile semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14648778A JPS5574180A (en) 1978-11-29 1978-11-29 Non-volatile memory

Publications (2)

Publication Number Publication Date
JPS5574180A true JPS5574180A (en) 1980-06-04
JPS5732513B2 JPS5732513B2 (en) 1982-07-12

Family

ID=15408735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14648778A Granted JPS5574180A (en) 1978-11-29 1978-11-29 Non-volatile memory

Country Status (1)

Country Link
JP (1) JPS5574180A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723921A (en) * 1980-07-21 1982-02-08 Teijin Ltd Light wavelength-converting polycarbonate structure
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5723921A (en) * 1980-07-21 1982-02-08 Teijin Ltd Light wavelength-converting polycarbonate structure
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Also Published As

Publication number Publication date
JPS5732513B2 (en) 1982-07-12

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