JPS557022B1 - - Google Patents

Info

Publication number
JPS557022B1
JPS557022B1 JP3140668A JP3140668A JPS557022B1 JP S557022 B1 JPS557022 B1 JP S557022B1 JP 3140668 A JP3140668 A JP 3140668A JP 3140668 A JP3140668 A JP 3140668A JP S557022 B1 JPS557022 B1 JP S557022B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3140668A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3140668A priority Critical patent/JPS557022B1/ja
Priority to US822484A priority patent/US3621564A/en
Publication of JPS557022B1 publication Critical patent/JPS557022B1/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/11001Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
    • H01L2224/11003Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for holding or transferring the bump preform
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111Tin [Sn] as principal constituent
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    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
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    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
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    • H01L2924/01006Carbon [C]
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    • H01L2924/01013Aluminum [Al]
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    • H01L2924/01024Chromium [Cr]
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    • H01L2924/0103Zinc [Zn]
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    • H01L2924/01033Arsenic [As]
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    • H01L2924/01042Molybdenum [Mo]
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    • H01L2924/01047Silver [Ag]
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    • H01L2924/0105Tin [Sn]
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    • H01L2924/01074Tungsten [W]
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    • H01L2924/01078Platinum [Pt]
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    • H01L2924/01079Gold [Au]
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    • H01L2924/01082Lead [Pb]
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    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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    • H01L2924/014Solder alloys
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    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01ELECTRIC ELEMENTS
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/166Material
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
JP3140668A 1968-05-10 1968-05-10 Pending JPS557022B1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3140668A JPS557022B1 (ja) 1968-05-10 1968-05-10
US822484A US3621564A (en) 1968-05-10 1969-05-07 Process for manufacturing face-down-bonded semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3140668A JPS557022B1 (ja) 1968-05-10 1968-05-10

Publications (1)

Publication Number Publication Date
JPS557022B1 true JPS557022B1 (ja) 1980-02-21

Family

ID=12330359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3140668A Pending JPS557022B1 (ja) 1968-05-10 1968-05-10

Country Status (2)

Country Link
US (1) US3621564A (ja)
JP (1) JPS557022B1 (ja)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3886585A (en) * 1973-07-02 1975-05-27 Gen Motors Corp Solderable multilayer contact for silicon semiconductor
US4035526A (en) * 1975-08-20 1977-07-12 General Motors Corporation Evaporated solderable multilayer contact for silicon semiconductor
JPS58158950A (ja) * 1982-03-16 1983-09-21 Nec Corp 半導体装置
US4574331A (en) * 1983-05-31 1986-03-04 Trw Inc. Multi-element circuit construction
JPS6149432A (ja) * 1984-08-18 1986-03-11 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPS61196564A (ja) * 1985-02-25 1986-08-30 シーメンス、アクチエンゲゼルシヤフト フイルムキヤリヤ集積回路とその製造方法
JPS61196546A (ja) * 1985-02-25 1986-08-30 シーメンス、アクチエンゲゼルシヤフト フイルムキヤリヤ集積回路とその製造方法
CA1226966A (en) * 1985-09-10 1987-09-15 Gabriel Marcantonio Integrated circuit chip package
JPS636850A (ja) * 1986-06-26 1988-01-12 Toshiba Corp 電子部品の製造方法
JPS63160352A (ja) * 1986-12-24 1988-07-04 Semiconductor Energy Lab Co Ltd 半導体装置の実装方法
US4739917A (en) * 1987-01-12 1988-04-26 Ford Motor Company Dual solder process for connecting electrically conducting terminals of electrical components to printed circuit conductors
US4752027A (en) * 1987-02-20 1988-06-21 Hewlett-Packard Company Method and apparatus for solder bumping of printed circuit boards
JPS63304636A (ja) * 1987-06-05 1988-12-12 Hitachi Ltd はんだキヤリア及びその製法並びにこれを用いた半導体装置の実装方法
US5255840A (en) * 1989-12-26 1993-10-26 Praxair Technology, Inc. Fluxless solder coating and joining
US6471115B1 (en) 1990-02-19 2002-10-29 Hitachi, Ltd. Process for manufacturing electronic circuit devices
US6227436B1 (en) 1990-02-19 2001-05-08 Hitachi, Ltd. Method of fabricating an electronic circuit device and apparatus for performing the method
JPH0779191B2 (ja) * 1991-04-08 1995-08-23 株式会社東芝 立体配線板の製造方法
TW223184B (ja) * 1992-06-18 1994-05-01 Matsushita Electron Co Ltd
US5567648A (en) * 1994-08-29 1996-10-22 Motorola, Inc. Process for providing interconnect bumps on a bonding pad by application of a sheet of conductive discs
FR2736206B1 (fr) * 1995-06-30 1997-08-08 Commissariat Energie Atomique Procede de realisation d'un substrat d'interconnexion permettant de connecter une puce sur un substrat de reception
JP3297254B2 (ja) * 1995-07-05 2002-07-02 株式会社東芝 半導体パッケージおよびその製造方法
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
JP3263288B2 (ja) * 1995-09-13 2002-03-04 株式会社東芝 半導体装置
US6008071A (en) * 1995-09-20 1999-12-28 Fujitsu Limited Method of forming solder bumps onto an integrated circuit device
US5686318A (en) 1995-12-22 1997-11-11 Micron Technology, Inc. Method of forming a die-to-insert permanent connection
US6404063B2 (en) 1995-12-22 2002-06-11 Micron Technology, Inc. Die-to-insert permanent connection and method of forming
JP3642110B2 (ja) * 1996-06-11 2005-04-27 松下電器産業株式会社 電子部品の製造方法
JPH1070153A (ja) * 1996-08-26 1998-03-10 Hitachi Ltd 電子部品の接続方法
US5803344A (en) * 1996-09-09 1998-09-08 Delco Electronics Corp. Dual-solder process for enhancing reliability of thick-film hybrid circuits

Also Published As

Publication number Publication date
US3621564A (en) 1971-11-23

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