JPS5570056A - Preparation of thick film hybrid integrated circuit - Google Patents
Preparation of thick film hybrid integrated circuitInfo
- Publication number
- JPS5570056A JPS5570056A JP14342978A JP14342978A JPS5570056A JP S5570056 A JPS5570056 A JP S5570056A JP 14342978 A JP14342978 A JP 14342978A JP 14342978 A JP14342978 A JP 14342978A JP S5570056 A JPS5570056 A JP S5570056A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- portions
- properties
- solder
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To lower the resistance of conductor portions while eliminating solder encroaching properties, by forming multilayer wiring and circuit elements by means of printing, by coating a circuit element portion with glass, etc. and by plating the upper portions of conductor portions with copper by soaking a substrate in a chemical plating liquid. CONSTITUTION:Circuit elements, such as, a resistor 5, etc. are made up in such a manner that a lower conductor 2, an insulator 3 and an upper conductor 4 are built up on an insulating substrate 1 in alumina, etc. by means of the printing and baking of Ag-Pd paste and borosilicate lead glass, and ruthenium oxide resistance paste, etc. are printed and baked. A circuit element 5 portion is coated with glass or resin 7, and the portions, which are not covered with insulators 7, 3, of the upper conductor 4 and the lower conductor 2 are plated with copper 8 by immersing the substrate 1 in a chemical copper plating liquid. Thus, the impedance of the conductor portions 2, 4 is lowered while solder encroaching properties are eliminated, solder moistening properties are bettered, the connection of parts by means of soldering is made possible and an integrating degree can be improved.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14342978A JPS5570056A (en) | 1978-11-22 | 1978-11-22 | Preparation of thick film hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14342978A JPS5570056A (en) | 1978-11-22 | 1978-11-22 | Preparation of thick film hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5570056A true JPS5570056A (en) | 1980-05-27 |
Family
ID=15338509
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14342978A Pending JPS5570056A (en) | 1978-11-22 | 1978-11-22 | Preparation of thick film hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5570056A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117386A (en) * | 1985-11-16 | 1987-05-28 | 株式会社住友金属セラミックス | Low temperature sintered ceramic substrate |
| US5506447A (en) * | 1993-06-15 | 1996-04-09 | Fuji Electric Co., Ltd. | Hybrid integrated circuit |
-
1978
- 1978-11-22 JP JP14342978A patent/JPS5570056A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62117386A (en) * | 1985-11-16 | 1987-05-28 | 株式会社住友金属セラミックス | Low temperature sintered ceramic substrate |
| JPH0584680B2 (en) * | 1985-11-16 | 1993-12-02 | Sumitomo Metal Ceramics Inc | |
| US5506447A (en) * | 1993-06-15 | 1996-04-09 | Fuji Electric Co., Ltd. | Hybrid integrated circuit |
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