JPS556670A - Multiplication processor - Google Patents

Multiplication processor

Info

Publication number
JPS556670A
JPS556670A JP7956878A JP7956878A JPS556670A JP S556670 A JPS556670 A JP S556670A JP 7956878 A JP7956878 A JP 7956878A JP 7956878 A JP7956878 A JP 7956878A JP S556670 A JPS556670 A JP S556670A
Authority
JP
Japan
Prior art keywords
word
length
carry
adder
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7956878A
Other languages
Japanese (ja)
Inventor
Takashi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7956878A priority Critical patent/JPS556670A/en
Publication of JPS556670A publication Critical patent/JPS556670A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase a processing speed by making a check on whether multiplication can be omitted as much as possible, by finding the alternate value of the multiplication process by an adder circuit for single-word-length operands in its early stage by providing a multiplier circuit for single-word-length operands and the adder circuit.
CONSTITUTION: To multiply two-word-length multiplicands AH and AL by two- word-length multipliers BL and BH, carrier save adder 5 finds single-word-length products of AH and BL, and AL and BH when AH and AL, and BL and BH are set to registers 1 and 2 respectively. Further, carry proper gate adder 8, leak register 15 and shifter 10 are used to compute AL+BL and AL+BL/2 to determine sum K greater than product AL×BL, and AH×BL and AL×BH are added to sum K; and carry detection circuit 9 makes a check on the existence of the carry of the addition results and only when the carry exists, a multiplication process of AL×BL is carried out.
COPYRIGHT: (C)1980,JPO&Japio
JP7956878A 1978-06-30 1978-06-30 Multiplication processor Pending JPS556670A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7956878A JPS556670A (en) 1978-06-30 1978-06-30 Multiplication processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7956878A JPS556670A (en) 1978-06-30 1978-06-30 Multiplication processor

Publications (1)

Publication Number Publication Date
JPS556670A true JPS556670A (en) 1980-01-18

Family

ID=13693599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7956878A Pending JPS556670A (en) 1978-06-30 1978-06-30 Multiplication processor

Country Status (1)

Country Link
JP (1) JPS556670A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961892A (en) * 1982-09-29 1984-04-09 ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン Data processing circuit for quick calculation of linear forecast coefficient for call

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961892A (en) * 1982-09-29 1984-04-09 ナシヨナル・セミコンダクタ−・コ−ポレ−シヨン Data processing circuit for quick calculation of linear forecast coefficient for call
JPH0443280B2 (en) * 1982-09-29 1992-07-16 Nat Semiconductor Corp

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