JPS5561038A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5561038A
JPS5561038A JP13435178A JP13435178A JPS5561038A JP S5561038 A JPS5561038 A JP S5561038A JP 13435178 A JP13435178 A JP 13435178A JP 13435178 A JP13435178 A JP 13435178A JP S5561038 A JPS5561038 A JP S5561038A
Authority
JP
Japan
Prior art keywords
layer
patterning
type
manufacture
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13435178A
Other languages
Japanese (ja)
Inventor
Masanao Itoga
Moritaka Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13435178A priority Critical patent/JPS5561038A/en
Publication of JPS5561038A publication Critical patent/JPS5561038A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To obtain a wiring pattern of an alloy layer by patterning a copper layer on an Al layer on semiconductor substrate to etch Al selectively and subjecting it to heat treatment.
CONSTITUTION: An Al layer 5 is provided on an n-type layer 2 of a p-type Si substrate through preparing a window in SiO2 3 and Cu 6 is patterned thereon. Next, the Al layer 5 is subjected to plasma etching by means of CCl, and thus a double layer of Al and Cu is formed. Then, it is treated in an H2 atmosphere at about 450°C for about 30 minutes, leaving an alloy layer 7 of Al and Cu. Now, a patterning of Al and Cu is ready accurately before alloying according to this process, and a yield of the device is improved consequently.
COPYRIGHT: (C)1980,JPO&Japio
JP13435178A 1978-10-31 1978-10-31 Manufacture of semiconductor device Pending JPS5561038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13435178A JPS5561038A (en) 1978-10-31 1978-10-31 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13435178A JPS5561038A (en) 1978-10-31 1978-10-31 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5561038A true JPS5561038A (en) 1980-05-08

Family

ID=15126322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13435178A Pending JPS5561038A (en) 1978-10-31 1978-10-31 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5561038A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745925A (en) * 1980-08-04 1982-03-16 Ibm Method of forming conductor
JPS58133958U (en) * 1982-03-03 1983-09-09 アルプス電気株式会社 Electronic component support device
US5110759A (en) * 1988-12-20 1992-05-05 Fujitsu Limited Conductive plug forming method using laser planarization
US5527739A (en) * 1993-12-23 1996-06-18 Motorola, Inc. Process for fabricating a semiconductor device having an improved metal interconnect structure

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745925A (en) * 1980-08-04 1982-03-16 Ibm Method of forming conductor
JPS58133958U (en) * 1982-03-03 1983-09-09 アルプス電気株式会社 Electronic component support device
US5110759A (en) * 1988-12-20 1992-05-05 Fujitsu Limited Conductive plug forming method using laser planarization
US5527739A (en) * 1993-12-23 1996-06-18 Motorola, Inc. Process for fabricating a semiconductor device having an improved metal interconnect structure

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