JPS5552592A - Data writing method and field effect transistor used for fulfillment - Google Patents

Data writing method and field effect transistor used for fulfillment

Info

Publication number
JPS5552592A
JPS5552592A JP12635678A JP12635678A JPS5552592A JP S5552592 A JPS5552592 A JP S5552592A JP 12635678 A JP12635678 A JP 12635678A JP 12635678 A JP12635678 A JP 12635678A JP S5552592 A JPS5552592 A JP S5552592A
Authority
JP
Japan
Prior art keywords
gate
drain
layer
source
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12635678A
Other languages
Japanese (ja)
Other versions
JPS6225272B2 (en
Inventor
Minoru Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP12635678A priority Critical patent/JPS5552592A/en
Publication of JPS5552592A publication Critical patent/JPS5552592A/en
Publication of JPS6225272B2 publication Critical patent/JPS6225272B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To obtain ROM of high integration by decreasing a current at the time of programming by storing logical binary information in FET having a floating gate, by applying an electric field of a fixed level between the gate and source or drain of FET. CONSTITUTION:On substrate 1, source 2, drain 3 and field oxide film 4 are formed and insulating layer 5 of fixed thickness is also formed between films 4. At a position of layer 5 away from a drain 3 side, floating gate 6 of a metal is bonded, insulating layer 7 is formed to a fixed thickness on the upper layer of this gate 6 and that of layer 5 without applied gate 6, and control gate 8 is formed on this layer 7. Further, contact holes 3a and 2a are formed which penetrate layers 5 and 7 and then reach drain 3 and source 2 and between gate 8 and source 2 or drain 3, high- tension pulses of a fixed level are applied by turns to store binary information in FET forming ROM by a small current.
JP12635678A 1978-10-13 1978-10-13 Data writing method and field effect transistor used for fulfillment Granted JPS5552592A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12635678A JPS5552592A (en) 1978-10-13 1978-10-13 Data writing method and field effect transistor used for fulfillment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12635678A JPS5552592A (en) 1978-10-13 1978-10-13 Data writing method and field effect transistor used for fulfillment

Publications (2)

Publication Number Publication Date
JPS5552592A true JPS5552592A (en) 1980-04-17
JPS6225272B2 JPS6225272B2 (en) 1987-06-02

Family

ID=14933146

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12635678A Granted JPS5552592A (en) 1978-10-13 1978-10-13 Data writing method and field effect transistor used for fulfillment

Country Status (1)

Country Link
JP (1) JPS5552592A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412311A (en) * 1980-06-04 1983-10-25 Sgs-Ates Componenti Elettronici S.P.A. Storage cell for nonvolatile electrically alterable memory

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4412311A (en) * 1980-06-04 1983-10-25 Sgs-Ates Componenti Elettronici S.P.A. Storage cell for nonvolatile electrically alterable memory

Also Published As

Publication number Publication date
JPS6225272B2 (en) 1987-06-02

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