JPS5550658A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS5550658A
JPS5550658A JP12255278A JP12255278A JPS5550658A JP S5550658 A JPS5550658 A JP S5550658A JP 12255278 A JP12255278 A JP 12255278A JP 12255278 A JP12255278 A JP 12255278A JP S5550658 A JPS5550658 A JP S5550658A
Authority
JP
Japan
Prior art keywords
type
layer
aluminum
implanted
type impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12255278A
Other languages
Japanese (ja)
Inventor
Takeshi Suzuki
Junichi Takita
Isao Kojima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12255278A priority Critical patent/JPS5550658A/en
Publication of JPS5550658A publication Critical patent/JPS5550658A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PURPOSE: To enhance the forward dielectric voltage of a semiconductor device by providing a pattern of metallic film thereafter becoming part of a metallic electrode when forming a region including impurities different in conductivity type from a semiconductor layer in the layer and implanting ion with the pattern as a mask.
CONSTITUTION: A p-type impurity ion is implanted to both front and back surfaces of an n-type semiconductor substrate 1, the substrate 1 is then heat treated, a p+-type layer is formed thereon to thus from a p+np+-type junction structure. Then, aluminum or the like is selectively coated on the surface of the p+-type layer becoming a cathode layer, and n-type impurity ion is implanted thereto with the aluminum as a mask to thereby provide a shallow n+-type region to thus form a p+np+n junction structure of four layers. Then, aluminum is coated on the entire surface of the latter structure to thereby form a cathode electrode making contact with the n+-type region. Thus, no abnormal n-type impurity diffusion occurs to thereby improve the forward dielectric voltage for a thyristor or the like and it can eliminate a heat oxide film normally used so as to thereby simplify the fabricating steps.
COPYRIGHT: (C)1980,JPO&Japio
JP12255278A 1978-10-06 1978-10-06 Method of fabricating semiconductor device Pending JPS5550658A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12255278A JPS5550658A (en) 1978-10-06 1978-10-06 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12255278A JPS5550658A (en) 1978-10-06 1978-10-06 Method of fabricating semiconductor device

Publications (1)

Publication Number Publication Date
JPS5550658A true JPS5550658A (en) 1980-04-12

Family

ID=14838693

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12255278A Pending JPS5550658A (en) 1978-10-06 1978-10-06 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS5550658A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117666A (en) * 1983-11-30 1985-06-25 Toshiba Corp Thyristor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60117666A (en) * 1983-11-30 1985-06-25 Toshiba Corp Thyristor

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