JPS5549725A - Input/output bus fault detection processing circuit - Google Patents

Input/output bus fault detection processing circuit

Info

Publication number
JPS5549725A
JPS5549725A JP12153078A JP12153078A JPS5549725A JP S5549725 A JPS5549725 A JP S5549725A JP 12153078 A JP12153078 A JP 12153078A JP 12153078 A JP12153078 A JP 12153078A JP S5549725 A JPS5549725 A JP S5549725A
Authority
JP
Japan
Prior art keywords
fault
level
low
signal
stack
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12153078A
Other languages
Japanese (ja)
Inventor
Tomihisa Nishijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12153078A priority Critical patent/JPS5549725A/en
Publication of JPS5549725A publication Critical patent/JPS5549725A/en
Pending legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To restrain the influence of a fault to a minimum by providing a by-pass circuit which transfers a request acceptance signal to a low-level I/O controller in case that the stack fault occurs.
CONSTITUTION: Assuming that the FF in request acceptance signal selector switch SELSW7 is in a stack state and low-level I/O controller IOC issues processing request signal BSRQST4, request acceptance signal SELACK5 is not transferred as it is; and when bus available signal BUSAVL6 comes continuously, FF1 is not reset though it should be reset normally. As a result, "1" output is generated from gate GT4 of FLDET8, and SELACK5 is transferred to the low-level IOC through gates GT2 and GT3 of by-pass circuit BYPSCT9, and simultaneously, the stack fault is trnasferred to CCI through fault transfer line FLLN10.
COPYRIGHT: (C)1980,JPO&Japio
JP12153078A 1978-10-04 1978-10-04 Input/output bus fault detection processing circuit Pending JPS5549725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12153078A JPS5549725A (en) 1978-10-04 1978-10-04 Input/output bus fault detection processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12153078A JPS5549725A (en) 1978-10-04 1978-10-04 Input/output bus fault detection processing circuit

Publications (1)

Publication Number Publication Date
JPS5549725A true JPS5549725A (en) 1980-04-10

Family

ID=14813506

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12153078A Pending JPS5549725A (en) 1978-10-04 1978-10-04 Input/output bus fault detection processing circuit

Country Status (1)

Country Link
JP (1) JPS5549725A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175168A (en) * 1984-02-21 1985-09-09 Minolta Camera Co Ltd Data transmission control device in multi-cpu system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60175168A (en) * 1984-02-21 1985-09-09 Minolta Camera Co Ltd Data transmission control device in multi-cpu system

Similar Documents

Publication Publication Date Title
JPS5549729A (en) Data transfer system
JPS5793422A (en) Dma controller
JPS57117027A (en) Signal sending and receiving circuit
JPS5549725A (en) Input/output bus fault detection processing circuit
JPS54154946A (en) Control unit of common bus
JPS5494845A (en) Bus control unit for data delivery unit
JPS53105947A (en) Data transfer system by bank switching of memory
JPS5696313A (en) Bus control device of multiprocessor system
JPS54107234A (en) Information processing unit
JPS5338236A (en) Multi-computer system
JPS5450247A (en) Interrupt control system
JPS57125427A (en) Circuit for transmitting simultaneously command signal
JPS5672753A (en) Selective processor for occupation of common bus line
JPS55127651A (en) Fault recognition system of multiprocessor system
JPS54143035A (en) Queue overflow processing system
JPS5549759A (en) Signal processing system
JPS5599641A (en) Control system for printer
JPS55131846A (en) Communication processor
JPS5696311A (en) Bus centralized monitoring system
JPS57166623A (en) Channel device
JPS5566016A (en) Signal priority level determination circuit
JPS57209559A (en) Decentralized processing system
JPS5450246A (en) Overrun prevention system in interrupt processing
JPS54114937A (en) Bus scramble circuit
JPS5624633A (en) Key input control system