JPS5537648A - Instruction decoder circuit - Google Patents

Instruction decoder circuit

Info

Publication number
JPS5537648A
JPS5537648A JP11042278A JP11042278A JPS5537648A JP S5537648 A JPS5537648 A JP S5537648A JP 11042278 A JP11042278 A JP 11042278A JP 11042278 A JP11042278 A JP 11042278A JP S5537648 A JPS5537648 A JP S5537648A
Authority
JP
Japan
Prior art keywords
decoder
outputs
instruction
register
master
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11042278A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6246891B2 (enrdf_load_stackoverflow
Inventor
Takashi Sakao
Yoshiaki Daimatsu
Toshiaki Suzuki
Kazuaki Mayumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11042278A priority Critical patent/JPS5537648A/ja
Publication of JPS5537648A publication Critical patent/JPS5537648A/ja
Publication of JPS6246891B2 publication Critical patent/JPS6246891B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
JP11042278A 1978-09-07 1978-09-07 Instruction decoder circuit Granted JPS5537648A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11042278A JPS5537648A (en) 1978-09-07 1978-09-07 Instruction decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11042278A JPS5537648A (en) 1978-09-07 1978-09-07 Instruction decoder circuit

Publications (2)

Publication Number Publication Date
JPS5537648A true JPS5537648A (en) 1980-03-15
JPS6246891B2 JPS6246891B2 (enrdf_load_stackoverflow) 1987-10-05

Family

ID=14535351

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11042278A Granted JPS5537648A (en) 1978-09-07 1978-09-07 Instruction decoder circuit

Country Status (1)

Country Link
JP (1) JPS5537648A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592146A (ja) * 1982-06-29 1984-01-07 Fujitsu Ltd マイクロプログラム制御装置
CN102841776A (zh) * 1994-12-02 2012-12-26 英特尔公司 可以对复合操作数进行压缩操作的微处理器

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02253082A (ja) * 1989-03-24 1990-10-11 Tokai Rubber Ind Ltd コネクタ

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS592146A (ja) * 1982-06-29 1984-01-07 Fujitsu Ltd マイクロプログラム制御装置
CN102841776A (zh) * 1994-12-02 2012-12-26 英特尔公司 可以对复合操作数进行压缩操作的微处理器
US9015453B2 (en) 1994-12-02 2015-04-21 Intel Corporation Packing odd bytes from two source registers of packed data
US9116687B2 (en) 1994-12-02 2015-08-25 Intel Corporation Packing in destination register half of each element with saturation from two source packed data registers
US9141387B2 (en) 1994-12-02 2015-09-22 Intel Corporation Processor executing unpack and pack instructions specifying two source packed data operands and saturation
US9182983B2 (en) 1994-12-02 2015-11-10 Intel Corporation Executing unpack instruction and pack instruction with saturation on packed data elements from two source operand registers
US9223572B2 (en) 1994-12-02 2015-12-29 Intel Corporation Interleaving half of packed data elements of size specified in instruction and stored in two source registers
US9361100B2 (en) 1994-12-02 2016-06-07 Intel Corporation Packing saturated lower 8-bit elements from two source registers of packed 16-bit elements
US9389858B2 (en) 1994-12-02 2016-07-12 Intel Corporation Orderly storing of corresponding packed bytes from first and second source registers in result register

Also Published As

Publication number Publication date
JPS6246891B2 (enrdf_load_stackoverflow) 1987-10-05

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