JPS5531639A - Forming method for electric wiring - Google Patents
Forming method for electric wiringInfo
- Publication number
- JPS5531639A JPS5531639A JP10435378A JP10435378A JPS5531639A JP S5531639 A JPS5531639 A JP S5531639A JP 10435378 A JP10435378 A JP 10435378A JP 10435378 A JP10435378 A JP 10435378A JP S5531639 A JPS5531639 A JP S5531639A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- time
- current
- output
- over
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
PURPOSE: To facilitate high quality of etching homogeneously by deciding over- etching time from the thickness of electric conductive layer adhered on the substrate and the time unitl electric current flowing between two electrodes arrives at a settled current.
CONSTITUTION: When a wafer 2 has been put into an etching reservoir 1, a starting switch 17 is depressed, a timer 11 operates, at the same time, electrolytic etching current is amplified by an amplifier 10, which is sent to a processer 15, and compared with a value of a reference current setting circuit 13. When the etching current has been lessened smaller than the value of the reference current setting circuit 13. When the etching current the has been lessenes smaller than the valve of reference current setting circuit 13, the processor 15 calculates out etching extent per unitary time from output T of the timer 11 at that time and output of an initial thickness setting switch 12, the over-etching time T' is calculated out from said amount and output of an over-etching membrane thickness setting switch 14. And, the processer 15 displays that when the output of the timer 11 has become the value from the addition of said times T and T', the etching is over by setting a display unit ON.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10435378A JPS5531639A (en) | 1978-08-29 | 1978-08-29 | Forming method for electric wiring |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10435378A JPS5531639A (en) | 1978-08-29 | 1978-08-29 | Forming method for electric wiring |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5531639A true JPS5531639A (en) | 1980-03-06 |
| JPH0127572B2 JPH0127572B2 (en) | 1989-05-30 |
Family
ID=14378507
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10435378A Granted JPS5531639A (en) | 1978-08-29 | 1978-08-29 | Forming method for electric wiring |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5531639A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58141531A (en) * | 1982-02-18 | 1983-08-22 | Toshiba Corp | Semiconductor element metal thin film etching apparatus |
| US4621037A (en) * | 1984-07-09 | 1986-11-04 | Sigma Corporation | Method for detecting endpoint of development |
| US4755442A (en) * | 1985-08-19 | 1988-07-05 | Kabushiki Kaisha Toshiba | Pattern developing process and apparatus therefor |
| US6378199B1 (en) | 1994-05-13 | 2002-04-30 | Dai Nippon Printing Co., Ltd. | Multi-layer printed-wiring board process for producing |
| JP2011222790A (en) * | 2010-04-12 | 2011-11-04 | Fuji Electric Co Ltd | Method and apparatus for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5387667A (en) * | 1977-01-12 | 1978-08-02 | Hitachi Ltd | Detecting method for etching end point of non-conductive film |
-
1978
- 1978-08-29 JP JP10435378A patent/JPS5531639A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5387667A (en) * | 1977-01-12 | 1978-08-02 | Hitachi Ltd | Detecting method for etching end point of non-conductive film |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58141531A (en) * | 1982-02-18 | 1983-08-22 | Toshiba Corp | Semiconductor element metal thin film etching apparatus |
| JPH0316776B2 (en) * | 1982-02-18 | 1991-03-06 | Tokyo Shibaura Electric Co | |
| US4621037A (en) * | 1984-07-09 | 1986-11-04 | Sigma Corporation | Method for detecting endpoint of development |
| US4755442A (en) * | 1985-08-19 | 1988-07-05 | Kabushiki Kaisha Toshiba | Pattern developing process and apparatus therefor |
| US6378199B1 (en) | 1994-05-13 | 2002-04-30 | Dai Nippon Printing Co., Ltd. | Multi-layer printed-wiring board process for producing |
| JP2011222790A (en) * | 2010-04-12 | 2011-11-04 | Fuji Electric Co Ltd | Method and apparatus for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0127572B2 (en) | 1989-05-30 |
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