JPS5531375A - Signal transmission system - Google Patents
Signal transmission systemInfo
- Publication number
- JPS5531375A JPS5531375A JP10521278A JP10521278A JPS5531375A JP S5531375 A JPS5531375 A JP S5531375A JP 10521278 A JP10521278 A JP 10521278A JP 10521278 A JP10521278 A JP 10521278A JP S5531375 A JPS5531375 A JP S5531375A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- time
- transmission
- delay
- transmission delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/05—Electric or magnetic storage of signals before transmitting or retransmitting for changing the transmission rate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Communication Control (AREA)
Abstract
PURPOSE:To make the same clock unnecessary to the whole system and to make it possible to avoid an error based on transmission delay by use of a simple device, by checking transmission delay with the repeating installation only. CONSTITUTION:When the transmission line 2 into which the repeating installation 3 has been inserted is commonly used by several signal generation device 1, and there exists a signal input exceeding the transmission capacity of the transmission line 2, the overflowing signal is stored in the buffer memory 21 of the device 3 and is made to wait, while the device 1 performs retransmission or demand unless there is a response within a given period of time. And when the delay time from input to output to the device 3 is a signal exceeding the fixed value, or the time until the signal reaches one device 1 from the other device 1 is less than the fixed value, comparing with the time to transmit the signal to the other device 1 from one device 1, the latter signal is abandoned. Thus the same clock can be made unnecessary to the whole system, and the error based on transmission delay can be avoided by use of a simple device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10521278A JPS5531375A (en) | 1978-08-29 | 1978-08-29 | Signal transmission system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10521278A JPS5531375A (en) | 1978-08-29 | 1978-08-29 | Signal transmission system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5531375A true JPS5531375A (en) | 1980-03-05 |
Family
ID=14401351
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10521278A Pending JPS5531375A (en) | 1978-08-29 | 1978-08-29 | Signal transmission system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5531375A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60190049A (en) * | 1984-03-12 | 1985-09-27 | Toshiba Corp | Packet communication equipment |
JPS62175053A (en) * | 1985-10-30 | 1987-07-31 | Fujitsu Ltd | Multichannel packet receiving system |
-
1978
- 1978-08-29 JP JP10521278A patent/JPS5531375A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60190049A (en) * | 1984-03-12 | 1985-09-27 | Toshiba Corp | Packet communication equipment |
JPS62175053A (en) * | 1985-10-30 | 1987-07-31 | Fujitsu Ltd | Multichannel packet receiving system |
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