JPS5739446A - Communication control device - Google Patents

Communication control device

Info

Publication number
JPS5739446A
JPS5739446A JP55113862A JP11386280A JPS5739446A JP S5739446 A JPS5739446 A JP S5739446A JP 55113862 A JP55113862 A JP 55113862A JP 11386280 A JP11386280 A JP 11386280A JP S5739446 A JPS5739446 A JP S5739446A
Authority
JP
Japan
Prior art keywords
character
receiving
shift register
request
control part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55113862A
Other languages
Japanese (ja)
Inventor
Kazuo Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55113862A priority Critical patent/JPS5739446A/en
Publication of JPS5739446A publication Critical patent/JPS5739446A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Abstract

PURPOSE:To execute the processing efficiently, by providing a means for informing that the next receiving character is stored before a high rank device receives a receiving character stored in a buffer register, which is so called as generation of receiving overrun. CONSTITUTION:A shift register 4 stores a data of one character portion through a circuit interface receiver 3 from a communication circuit 2. When a receiving character is stored, the shift register 4 outputs a character transfer request to a control part 5. When the control part 5 receives this request, it outputs a command to a comparing circuit 6, and makes it compare the previous receiving character in a character buffer 8 with the present receiving character in the shift register 4. After the comparison has ended, the control part 5 transfers the character to the character buffer 8 from the shift register 4, and simultaneosly set the result of comparisn to a status register 10. As a result of comparison, in case of dissidence, an overrun bit R of the status register 10 is set. When a high rank device 12 has received an interruption request, if R has been set, a retransmission request is outputted.
JP55113862A 1980-08-19 1980-08-19 Communication control device Pending JPS5739446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55113862A JPS5739446A (en) 1980-08-19 1980-08-19 Communication control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55113862A JPS5739446A (en) 1980-08-19 1980-08-19 Communication control device

Publications (1)

Publication Number Publication Date
JPS5739446A true JPS5739446A (en) 1982-03-04

Family

ID=14622947

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55113862A Pending JPS5739446A (en) 1980-08-19 1980-08-19 Communication control device

Country Status (1)

Country Link
JP (1) JPS5739446A (en)

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