JPS54100604A - Multi-link error control system - Google Patents
Multi-link error control systemInfo
- Publication number
- JPS54100604A JPS54100604A JP709378A JP709378A JPS54100604A JP S54100604 A JPS54100604 A JP S54100604A JP 709378 A JP709378 A JP 709378A JP 709378 A JP709378 A JP 709378A JP S54100604 A JPS54100604 A JP S54100604A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- check
- node
- sel
- inputted
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To improve transmission efficiency by making preceding node information ineffective in case of occurrence of a transmission error and then by adding a new check code. CONSTITUTION:A data block transmitted from preceding node A is inputted from selector circuit SEL(1) to check CHK and result R is fed back to SEL(1), thereby using the circuit as generator GEN this time. Data from the preceding node, on the other hand, are stored temporarily in buffer memory BFM and then sent out from selector circuit SEL(2) with the check result added. Without being inputted to check circuit CHK, data until the node two stages ahead are transmitted by timing control circuit CTLTIM directly from the gata circuit to next node B.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP709378A JPS54100604A (en) | 1978-01-25 | 1978-01-25 | Multi-link error control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP709378A JPS54100604A (en) | 1978-01-25 | 1978-01-25 | Multi-link error control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54100604A true JPS54100604A (en) | 1979-08-08 |
Family
ID=11656455
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP709378A Pending JPS54100604A (en) | 1978-01-25 | 1978-01-25 | Multi-link error control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54100604A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57118456A (en) * | 1981-01-14 | 1982-07-23 | Toshiba Corp | Data collecting system |
-
1978
- 1978-01-25 JP JP709378A patent/JPS54100604A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57118456A (en) * | 1981-01-14 | 1982-07-23 | Toshiba Corp | Data collecting system |
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