JPS55153460A - Logic circuit for transmission and reception - Google Patents

Logic circuit for transmission and reception

Info

Publication number
JPS55153460A
JPS55153460A JP6128479A JP6128479A JPS55153460A JP S55153460 A JPS55153460 A JP S55153460A JP 6128479 A JP6128479 A JP 6128479A JP 6128479 A JP6128479 A JP 6128479A JP S55153460 A JPS55153460 A JP S55153460A
Authority
JP
Japan
Prior art keywords
signal
confirming
data signal
adder
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6128479A
Other languages
Japanese (ja)
Other versions
JPS5932937B2 (en
Inventor
Shigeo Nakajima
Tatsuro Shomura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54061284A priority Critical patent/JPS5932937B2/en
Publication of JPS55153460A publication Critical patent/JPS55153460A/en
Publication of JPS5932937B2 publication Critical patent/JPS5932937B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying

Abstract

PURPOSE:To reduce the error rate of reproduced data signal, by logical conversion of original data signal and demodulated data signal through the use of confirming signal independent of the input data. CONSTITUTION:The confirming signal produced at the confirming signal generator 12 is logic-converted at the delay unit 13 and the adder 14-2, the converted output signal (b) is added to the original data signal (a) at the adder 14-1 to obtain the modulated data signal (c). The output of the oscillator 16 is phase-modulated 15 with the signal (c) to produced modulation wave. This modulation signal is demodulated at the demodulator 19 and the demodulated data signal (d) is obtained with the discrimination of 0,1 at the discriminator 21. The confirming signal only is extracted at the confirming signal extracting circuit 22, and the inverse logical operation is received from the transmission side at the adders 23-3 and 23-4 and delay unit 24 and it is input to the confirming signal error detection circuit 25. The circuit 25 detects the confirming signal in error on the transmission line to output the error correction pulse, and the error is corrected at the adder 23-2 and the result is added with the signal d at the adder 23-1 to produce correct reproduced data signal.
JP54061284A 1979-05-18 1979-05-18 Transmission/reception logic circuit Expired JPS5932937B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54061284A JPS5932937B2 (en) 1979-05-18 1979-05-18 Transmission/reception logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54061284A JPS5932937B2 (en) 1979-05-18 1979-05-18 Transmission/reception logic circuit

Publications (2)

Publication Number Publication Date
JPS55153460A true JPS55153460A (en) 1980-11-29
JPS5932937B2 JPS5932937B2 (en) 1984-08-11

Family

ID=13166740

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54061284A Expired JPS5932937B2 (en) 1979-05-18 1979-05-18 Transmission/reception logic circuit

Country Status (1)

Country Link
JP (1) JPS5932937B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4819750A (en) * 1988-02-16 1989-04-11 Sunbeam Corporation Electronic bath scale

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS537762A (en) * 1976-07-09 1978-01-24 Katashi Aoki Method and device for high speed opening and shutting mold of injection molder

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS537762A (en) * 1976-07-09 1978-01-24 Katashi Aoki Method and device for high speed opening and shutting mold of injection molder

Also Published As

Publication number Publication date
JPS5932937B2 (en) 1984-08-11

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