JPS6141462B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modulation method for binary AMI code strings.

The binary AMI code is a code format in which the NRZ code “1” corresponds to “0,1” or “1,0”, and “0” corresponds to “1,1” or “0,0”. It has the features of being rich in information, not containing DC components, not having the same level consecutively for more than 3/2 slots, and not losing the original information when swapping the upper and lower levels. It has been widely applied. However, this code format requires two frequency bands compared to the NRZ code.
This is difficult to use when the transmission line bandwidth is small, and when other signals such as monitoring signals are superimposed on the binary AMI signal in a time-sharing manner, an even larger transmission line bandwidth is required. There are drawbacks such as the need for

An object of the present invention is to compensate for the above-mentioned drawbacks of the binary AMI code and to enable superimposition of other signals without increasing the required frequency band of the binary AMI code.

Therefore, the present invention provides a binary AMI signal (NRZ “1”)
“1,0” or “0,1” corresponds to “0”
This binary AMI is created by superimposing a modulated signal on
Modulate the signal by forcing an error, transmit this modulated signal, obtain a demodulated signal from this modulated signal on the receiving side, demodulate the received modulated signal using the demodulated signal, and transmit the modulated signal on the receiving side. This is to obtain the original binary AMI signal. Specific examples thereof will be described in detail below with reference to the accompanying drawings.

FIG. 1 is a time chart for explaining the code modulation method of the present invention, and shows output waveforms of various parts of the code modulation circuit shown in FIG. 2 and the demodulation circuit shown in FIG. 3.

In Fig. 2, 1 is a binary AMI signal generator;
2 is the binary value output from the binary AMI signal generator 1
This is a modulation signal generator that generates a modulation signal at the timing of the first half phase of the signal unit S of the AMI signal a, and is synchronized with the output clock of the binary AMI signal generator 1. In this embodiment, the pulse width of the modulation signal b is half the signal unit S of the binary AMI signal a. Reference numeral 3 denotes a modulator which takes the exclusive OR of the output signals a and b of the binary AMI signal generator 1 and the modulated signal generator 2 and gives an error to the binary AMI code. Reference numeral 4 denotes a demodulator provided on the receiving side, and its specific configuration is as shown in FIG. 5 is modulator 3
The binary AMI signal c from and the output g from the demodulator 4
The modulator 3 is an error corrector that removes the added error. Also,
In the demodulation circuit shown in Figure 3, 6 is the received binary value
Delay circuit that delays AMI signal c by half a bit, 7
8 is the timing extraction circuit that outputs the clock signal f, and 8 is the output d of the delay circuit 6 and the binary AMI signal c.
9 is a NOR element that negates the output of exclusive OR element 8;
10 is an AND element which takes the logical product of the output of the NOR element 9 and the output of the timing extraction circuit 7.

In FIG. 2, the output a of the binary AMI signal generator 1 corresponds to the output b of the modulation signal generator 2.
When inverting by half a bit in modulator 3, we get
A signal c as shown in FIG. 1 is output.
This is transmitted via a transmission line, and on the receiving side,
The signal delayed by half a bit by the delay circuit 6 of the demodulator shown in FIG. 3 and the received signal are ORed by 8 exclusive OR elements to obtain an output e. This output e is inverted by NOR element 9, and AND element 10
Then, the negative output and the clock signal f from the timing extraction circuit 7 are ANDed to obtain a demodulated signal g.

On the other hand, the error corrector 5
By taking the exclusive OR of the AMI signal e and the demodulated signal g from the demodulator 4, a signal h as shown in FIG. 1 is obtained, but this signal h is the original binary
Since it is equal to the AMI signal a, it is possible to compensate for errors in the binary AMI signal. In addition, as mentioned above, 2
Inverting half the bits of the value AMI signal creates a binary AMI
When converting a signal into an NRZ signal, the NRZ signal will always have one bit error, so even if the converted NRZ signal is inverted in accordance with the output g of the demodulator 4, the original error-free NRZ signal will not be returned. can get.

The demodulator 4 is a necessary circuit for monitoring errors in transmission line codes, and the exclusive logic element configuring the error corrector 5 shown in FIG. 2 and the exclusive logic element shown in FIG. Binary AMI just by adding 8
Other signals can be superimposed on the signal.

As is clear from the above description, according to the present invention, other signals can be superimposed by simply adding a simple circuit without increasing the frequency band while maintaining the advantages of the binary AMI code.

[Brief explanation of the drawing]

The attached drawings show one embodiment of the present invention; FIG. 1 is a time chart for explaining the binary AMI code modulation of the present invention, FIG. 2 is a specific block configuration diagram of the code modulation circuit, FIG. 3 is a partially detailed circuit diagram of FIG. 2. 1... Binary AMI signal generator, 2... Modulation signal generator, 3... Modulator, 4... Demodulator, 5... Error corrector, 6... Delay circuit, 7... Timing extraction circuit , 8... exclusive OR element, 9...
NOR element, 10...AND element.

Claims (1)

[Claims] 1. A binary AMI signal generator that generates a binary AMI signal; a modulation signal generator that generates a modulation signal in the first half phase of a signal unit of the binary AMI signal;
Modulation in which an exclusive OR of the AMI signal and the modulated signal is taken, and the binary AMI signal of the binary AMI signal generator is modulated to form a modulated signal, which is then sent to the transmission path. The modulated signal received from the transmission path and the signal delayed by half a bit are inverted, and the output is ANDed with the clock signal to perform demodulation. a demodulator that obtains the signal; and a demodulator that calculates the exclusive OR of the modulated signal and the demodulated signal to obtain the binary
A binary AMI code modulation method comprising an error corrector that outputs an AMI signal.