JPS6046582B2 - Sub signal superimposition transmission method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sub-signal superimposition transmission system in which a pulse signal such as a PCM signal is used as a main signal, and sub-signals for monitoring, meetings, etc. are superimposed on the main signal and transmitted.

In the transmission of digital signals such as PCM signals, the transmission speed of pulses is fixed, and on the receiving side, a timing component equal to the transmission speed is extracted from the received pulse train and a clock pulse synchronized with it is regenerated.

This method of transmitting sub-signals such as monitoring and meeting signals in addition to main signals such as PCM signals is based on the fact that the bandwidth of sub-signals such as monitoring and meeting signals is generally sufficiently low compared to the transmission band of main signal pulses. It is possible to focus on a method in which the transmission frequency or pulse phase of the main signal is shallowly modulated by the sub-signal. However, in this case, a stable lock regeneration circuit is required on the receiving side to detect the modulated frequency or phase. Furthermore, in order to branch and insert the monitoring meeting signal through multi-relay transmission, it is necessary to always generate clock pulses that are not affected by modulation, and a highly stable circuit is required. SUMMARY OF THE INVENTION An object of the present invention is to provide a sub-signal superimposition method using pulse width modulation, which can reproduce clock pulses using a simple circuit as in the conventional method.

The sub-signal superimposition transmission method of the present invention uses a digital signal such as a PCM signal as a main signal, and includes a transmitter including a pulse width modulator that changes the pulse width of the main signal pulse according to the sub-signal, and a rising edge detecting means for receiving the modulated pulse, detecting a rising edge of the received waveform and outputting a rising edge detection pulse signal, and a falling edge detecting means for detecting a falling edge of the received waveform and outputting a falling edge detection pulse signal; a first clock regeneration circuit that extracts a clock component from the rising edge detection pulse signal and reproduces a first clock signal;
a second clock regeneration circuit that regenerates the clock signal;
The transmission method includes a phase comparator that compares the phases of the first and second clock signals, and a comparison output of the phase comparator becomes a received sub-signal.

According to the present invention, the trailing edge of the main signal pulse changes due to pulse width modulation, but the leading edge does not, so that the clock pulse can be easily reproduced from the leading edge.

Since the frequency or phase of the clock itself is not modulated, the clock pulse can be reproduced with a simple circuit. Next, the present invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the transmitting section of the present invention. A indicates a main signal pulse train input signal subjected to density modulation, B indicates a sub-signal input for monitoring, meetings, etc., and 1 indicates a pulse width modulator. C is the pulse width modulated modulated pulse output. Embodiments of the pulse width modulator 1 are shown in FIGS. 3 and 4. In FIG. 3, when the main signal pulse train A shown in FIG. 5A and the binary pulse shown in FIG. 5B as a sub signal are input to the pulse width modulator, the main signal pulse A is is input to the AND gate with a delay of T time. At this time, if the sub signal is "1", the main signal pulse A passes through the AND gate and enters the 0R gate.If the pulse width of the main signal is T or more, this T
Due to the time-delayed main signal pulse, the pulse width of the modulated pulse C is increased by T time. Also. If the sub-signal is ゛゜0゛, no AND output is output, and therefore the main signal pulse C is output without any increase in time T. Therefore, only the trailing edge of the main signal pulse that arrives at the time when the sub signal B is "1" increases by the time T.

Therefore, the pulse modulated by the sub-signal has the pattern shown in FIG. 5C. FIG. 4 shows a pulse width modulator when an analog waveform is input as a sub-signal. The flip-flop 7 is set by the rising edge of the main signal pulse A. The output generates a triangular wave with a constant slope in the triangular wave generator 8, and when the amplitude of the triangular wave and the sub-signal B intersect, the flip-flop 7 is reset and the triangular wave is also reset by the output. Therefore, the output of the flip-flop 7 becomes a pulse whose rise occurs at the leading edge of the main signal pulse, and whose fall point changes due to the subtraction of the sub-signal B, and this output is output as the main signal pulse C. Second
The figure shows an embodiment of the receiving section in the present invention.

A modulated pulse C'' that has been subjected to pulse width modulation is received and input to a rising differential circuit 2 and a falling differential circuit 3.The transmitter shown in FIG. 1 sends out a main signal pulse C in which only the falling portion has changed. Therefore, only the falling portion of the received pulse C'' changes temporally. The output of the rising differential circuit 2 becomes an output D that is not affected by pulse width modulation. Further, the output of the falling differentiation circuit 3 becomes an output E whose phase changes due to pulse width modulation. In the clock regeneration circuit 4 which extracts the clock component of the main signal A from the differential output D, a clock pulse F is generated.
is played and output. Using the differential output E, the clock reproducing circuit 5 extracts and outputs a clock component G whose phase changes due to pulse width modulation. In this case, the clock regeneration circuit 5 is composed of a bandpass filter with a bandwidth corresponding to the sub-signal band and a waveform shaping circuit.The clock output has a constant phase clock pulse F and a clock output whose phase has been varied by pulse width modulation. Phase comparison with G is performed by the phase comparator 6, and the waveform shown in FIG. 5B is output as the phase comparison output B''.

That is, this clock output G and clock pulse F
is input to the phase comparator 6 as a waveform with a constant amplitude, a phase comparison output B'' proportional to the pulse width change of the modulated pulse C is outputted. The other components have been removed. Therefore, this phase comparison output B'' becomes the received signal of the sub signal B. Although it is necessary to use a phase comparator with good linearity for analog waveform transmission, pulse transmission is less affected by waveform distortion due to nonlinearity and amplitude fluctuations of the clock output G. Therefore, in the present invention, sub-signals can be received with a simple configuration in which a clock extraction circuit and a phase comparator are newly added to the conventional various reproduction circuit.

In the description of the embodiment, the trailing edge portion of the pulse is modulated in width, but this is the same as modulating the leading edge portion.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the transmitting section of the present invention, FIG. 2 is a block diagram of an embodiment of the receiving section of the present invention, FIG. 3 is a circuit diagram showing a pulse width modulator of the transmitting section of the present invention, and FIG. The figure shows a block diagram of the pulse modulator of the transmitter of the present invention, and FIG. 5 shows a time chart of the pulse signal pattern. 1... Pulse width modulator, 2... Rising differential circuit, 3
・Falling differentiation circuit, 4, 5...clock regeneration circuit, ・
...Phase comparator.

Claims (1)

[Claims] 1. A transmitter including a pulse width modulator that uses a digital signal such as a PCM signal as a main signal and changes the pulse width of the main signal pulse according to a sub signal, and receives a modulated pulse from the transmitter. a rising edge detection means for detecting a rising edge of a waveform and outputting a rising edge detection pulse signal; a falling edge detecting means for detecting a falling edge of the received waveform and outputting a falling edge detection pulse signal; and a clock component detected from the rising edge detection pulse signal. a first clock regeneration circuit that extracts a clock component from the falling detection pulse signal and regenerates the first clock signal; a second clock regeneration circuit that extracts a clock component from the falling detection pulse signal and regenerates a second clock signal; and a phase comparator for comparing the phases of a second clock signal, and a comparison output of the phase comparator is a received sub-signal.