JPS6367851A - Transmission system for frame synchronizing signal - Google Patents

Abstract

PURPOSE:To decode a multidimensional code by sending out an offset at a signal point position additionally from a transmission side at the time of a symbol indicating the transmission of a frame synchronizing signal and detecting the frame synchronizing signal on a reception side based on an error quantity from a reference signal point. CONSTITUTION:When the frame synchronizing signal is sent out on the transmission side, a constant offset a is added by adders 2 and 3 to an amplitude and a phase component at a sent signal point and the signal is sent out. A synchronous detecting circuit 24 on the reception side finds the quantities of errors between the amplitude and phase component of a received signal and the amplitude and phase component of a reference signal and integrates the sum of the absolute values of the error quantities by one symbol. Then it is decided that there is the frame synchronizing signal in a symbol which is larger than a reference value among successively generated 1-symbol integral values. Only when the frame signal is found, adders 25 and 26 subtract the offset alpha from the (x) component and (y) component of the position signal at a received signal point and when no frame synchronizing signal is found, 0 is subtracted and a decision device 27 decides the received signal point to decode the multidimensional code.

Description

[Detailed Description of the Invention] [Summary] In a modem for data transmission, when a symbol is used to send a frame synchronization signal, the transmitting side adds a certain offset to the signal point position and sends it out, and the receiving side adds a certain offset to the signal point position and sends it out, and the receiving side uses a reference signal. A frame synchronization signal is detected based on the amount of error from the point.

[Industrial application field]

The present invention relates to a frame synchronization signal transmission method in a data communication modem that employs a multidimensional encoding method.

[Conventional technology]

As is well known, when it comes to high-speed modems, the number of signal points arranged in one symbol, which is one piece of modulation information, increases, and as a result, the distance between signal points becomes shorter, making it easier to be affected by noise. be.

To prevent this, there is a multidimensional coding method that increases the distance between signal points.

FIG. 4 is an explanatory diagram of the multidimensional encoding method.

Conventional coding methods transmit each symbol, but
In this system, as shown in (2) in FIG. 4, transmission data is collected into n symbols (n is plural) and transmitted with a certain regularity given to the data between these n symbols. Therefore, since demodulation is also performed in n-symbol units, the receiving side requires a frame synchronization signal indicating the start of a block every n symbols, as shown in (■) in FIG. Without this frame synchronization signal, it is not possible to demodulate receiver data as shown in (■) in FIG.

[Problem that the invention seeks to solve]

The object of the present invention is to provide a frame synchronization signal system for realizing the above-mentioned multidimensional encoding.

[Means for solving problems]

The above-mentioned problem is a data communication modem that uses a multidimensional encoding method as shown in the principle diagram in Figure 1, and on the transmitting side, when transmitting a frame synchronization signal, the amplitude and phase of the transmitting signal point An adder 2.3 adds a certain offset α to each component and sends it out, and on the receiving side, the amount of error between the amplitude and phase components of the received signal and the amplitude and phase components of the reference signal is determined, Find the sum of the absolute values of the error amounts, and set the sum to 1
This problem can be solved by providing a synchronization detection circuit 24 that integrates symbols and determines that a frame synchronization signal is present in a symbol that is equal to or higher than a reference value among the integrated values for a plurality of consecutively occurring l symbols. Ru.

[Effect]

According to the present invention, on the transmitting side, when a symbol is used to transmit a frame synchronization signal, the adder 2.3 adds a certain offset α to the amplitude and phase components of the position signal of the transmitting signal point. On the transmitting and receiving sides, the synchronization detection circuit 24 detects a frame synchronization signal, and only when this detected frame signal is output, the adders 25 and 26 offset the X component of the position signal of the received signal point and the X component. After subtracting α and subtracting 0 when the frame synchronization signal is not output,
The determiner 27 determines the received signal point and decodes the multidimensional code.

〔Example〕

FIG. 2(a) is a diagram showing an embodiment of the configuration of equipment on the transmitting side of the frame signal transmission method according to the present invention.

FIG. 2(b) is a diagram showing an embodiment of the configuration of receiving side equipment of the frame signal transmission system according to the present invention.

FIG. 2(C) is a diagram showing an embodiment of the synchronization detection circuit according to the present invention.

FIG. 3 is an explanatory diagram of the present invention.

In the figure, 1 is a signal point generation circuit, 2 and 3 are adders, 4 is a roll-off filter (ROF), 5 is a modulator, and 6
is a filter (FIL), 7 is a carrier generator, 8 is a transmit baud rate clock, 9 is a frequency divider, 10 is a switch, 20 is a demodulator, 21 is a roll off filter (RO
F), 22 is an automatic isograph, 23 is a carrier APC circuit,
24 is a synchronization detection circuit, 25 and 26 are adders, 27 is a judger, 28 is a multidimensional code demodulator, 30 is a buffer, 3
1.32 is an adder, 33.34 is an absolute value, 35
is an adder, 36.38.41 is a multiplier, 37.39.4
2 is an adder, 40 is a delay element, 43 is a frame signal output circuit, and 50 is an integration circuit.

In the present invention, in order to transmit a frame synchronization signal, n
Give a constant offset to the signal point position for each symbol.

FIGS. 3(a) and 3(b) are explanatory diagrams when the number of signal points arranged is 4. The given signal point positions are shown in FIG. 3 (the x marks in bl indicate the signal point positions in the normal state).

A constant offset can be realized, for example, by applying a constant DC voltage α in the X direction and the Y direction and shifting the signal point position as shown in FIG.

On the transmitting side, as shown in FIG. 2(a), the transmitting data SD and the clock of the transmitting baud rate I~ clock 8 output are input to the signal point generating circuit 1, and the transmitting data S is inputted from the signal point generating circuit 1.
Outputs the X component and the X component of the D signal. The X component of the signal is sent to adder 2, and the X component of the signal is sent to adder 3.

On the other hand, the output clock of the transmitting baud rate clock 8 is sent to the frequency divider 9, where it is frequency-divided and sent to the switch 1 once every n symbols.
Drive 0.

Normally, the switch 10 is connected to the "0" side, so it outputs a constant O to the adder 2.3.
The switch 10 operates to connect to the "α" side. For this purpose, a constant α is sent to adder 2.3.

Therefore, adders 2.3 and 2.3 both add the X component of each signal,
Add a constant 0 to the component and output it (output its value), but once every n symbols, adder 2 adds a constant α to the X component and outputs it, and adder 3 adds α to the X component. and output it.

Both the output of adder 2 and the output of adder 3 are modulated by modulator 5 after unnecessary frequency components are removed by ROF 4.
It is sent to the receiving side via FIL6.

In this way, on the transmitting side, a fixed offset is given to the signal and transmitted once every n symbols.

On the receiving side, as shown in Figure 2 (bl), after demodulating with a demodulator 20, unnecessary frequency components are removed with an ROF 21, and automatic The signal is equalized by a circuit 2E and passed through a carrier APC circuit 23 to remove the influence of noise.

At this stage, the frame synchronization signal is input to the synchronization detection circuit 24 in order to detect it.

FIG. 2(C) is a diagram showing an embodiment of the synchronization detection circuit 24 according to the present invention.

The output of the X component of the carrier APC circuit 23 is converted to a certain reference value x9. is subtracted. Similarly carrier APC
The output of the X component of the circuit 23 is set to a certain reference value yr by the adder 32.
af is subtracted. x−xr, f, and Y Yr*t
are sent to absolute values 33 and 34, respectively, and their absolute values are calculated here.

Both absolute values are added by an adder 35, and by this operation, the coordinates (x, y) of the receiving point and a certain reference point (X□.

, y□, ) is determined. This amount of error is sent to the integrating circuit 50.

The integrating circuit 50 includes three adders 37 as shown in the second (C).
．． It is composed of 39, 42, and 3 multipliers 36, 38, and 41, and a delay element 40, and integrates the error amount of each symbol, and the integrated value is cleared for each symbol.

After the output of the adder 35 is multiplied by a multiplier 36, a reference value Ref is added to it by an adder 37, and a certain constant α1 is added to it by a multiplier 38. Note that the process (2) is a preprocess for keeping the integral value within a desired range (to prevent the delay element 40 from overflowing) in the next integration process.

The output of the multiplier 38 is sent to an integrating circuit consisting of an adder 39 and a delay element 40, where it is integrated.

(2) The integral value of the output of the adder 39 is sent to a multiplier 41, where it is multiplied by a certain constant α2, and then sent to an adder 42, where a constant β is added. The output of this adder 42 is sent to the multiplier 36 described above and multiplied by the output of the adder 35. Processing (2) is performed for coefficient correction.

The output of the delay element 40 is transferred symbol by symbol to the buffer 30 and then cleared. The buffer 30 has a buffer for n symbols, and integral values for n symbols are transferred one after another.

For this reason, as shown in FIG. 3 (C1), only the buffer of the symbol--frame signal position--that is far away from the reference point will show a large value.Therefore, as shown in FIG. It becomes possible to detect a frame signal by connecting the values of each element of the buffer 30 at a certain threshold (indicated by a dotted line).

In this manner, the synchronization detection circuit 24 detects a frame signal, and when the frame signal is generated, the adder 25 and the adder 26 subtract the offset α from the signal point position to make the X component and the y component co-element. It can be returned. Note that when the frame signal is not output, minute and y component signals are input, and after the respective signal point positions are determined here, they are sent together with the frame signal to the multidimensional code decoder 28, where the received data RD will be returned to.

In this manner, correct determination and decoding can be performed by subtracting the offset α from the signal point of the carrier APC circuit 23 output only when a certain symbol of the frame signal detected by the synchronization detection circuit 24 is detected.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect of being able to transmit frame signals without changing the original data rate of the modem.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. Figure 2 (al is a diagram showing an example of the transmitting side equipment configuration of the frame signal transmission method according to the present invention. Figure 2 (bl is a diagram showing an example of the receiving side equipment configuration of the frame signal transmission method according to the present invention) FIG. 2(C) is a diagram showing an embodiment of the synchronization detection circuit 24 according to the present invention. FIG. 3 is an explanatory diagram of the present invention. FIG. It is an explanatory diagram of a multidimensional encoding system. In the figure, 1 is a signal point generation circuit, 2 and 3 are adders, 4 is a roll-off filter (ROF), 5 is a modulator, and 6
is a filter (FIL), 7 is a carrier generator, 8 is a transmission baud rate clock, 9 is a frequency divider, 10 is a switch,
20 is a demodulator, 21 is a roll-off filter (ROF)
), 22 is an automatic equalization layer, 23 is a carrier APC circuit, 2
4 is a synchronization detection circuit, 25 and 26 are adders, 27 is a determiner, 28 is a multidimensional code decoder, 30 is a buffer, 31
．． 32 is an adder, 33.34 is an absolute value, 35 is an adder, 36.38.41 is a multiplier, 37.39.42
is an adder, 40 is a delay element, 43 is a frame signal output circuit, and 50 is an integration circuit. Sending I Word I Rule (α Ji Cb) 1st Figure This issue, Sun Moon Juru Flem No. 48,
2, Teishiryo Kaname 5 ÷ 2 Composed of 1 pointed i Zenkakukyu lacquer 2 Zuzuzui 0 month Yorofu L-, spade and Butsucho 2 no Uke, Igo ii Katsuo φ Figure 2: Moon phase (8 times; 24 -l and 1C) Figure 2 ( C) Figure 3: Official diagram of the phantom dimension number 7 method Figure 4

Claims (1)

[Claims] A data communication modem employing a multidimensional encoding method, in which, on the transmitting side, when transmitting a frame synchronization signal, an adder (2, 3) is added to the amplitude and phase components of the transmitting signal point. ), a certain offset (α) is added to each signal and the signals are sent out. On the receiving side, the amount of error between the amplitude and phase components of the received signal and the amplitude and phase components of the reference signal is determined, and the amount of error is Find the sum of the absolute values, integrate the sum for one symbol, and if the frame synchronization signal is present in the symbol that is equal to or greater than a reference value among the cumulative values for a plurality of consecutive symbols, A synchronization detection circuit (24) for determining is provided, and only when the frame synchronization signal which is the output of the synchronization detection circuit (24) is output, the adder (25, 26) calculates the offset from the amplitude and phase components of the received signal. A frame synchronization signal transmission system characterized in that after subtracting (α), a receive signal point is determined by a determiner (27) and a multidimensional code is decoded.