JPH04196944A - Multilevel modulating/demodulating communication system - Google Patents
Multilevel modulating/demodulating communication systemInfo
- Publication number
- JPH04196944A JPH04196944A JP2327955A JP32795590A JPH04196944A JP H04196944 A JPH04196944 A JP H04196944A JP 2327955 A JP2327955 A JP 2327955A JP 32795590 A JP32795590 A JP 32795590A JP H04196944 A JPH04196944 A JP H04196944A
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- JP
- Japan
- Prior art keywords
- phase
- signal
- signal points
- phase plane
- bit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 238000006243 chemical reaction Methods 0.000 abstract description 14
- 230000005540 biological transmission Effects 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
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- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多値変復調通信方式に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a multilevel modulation/demodulation communication system.
変調信号の位相面に複数の信号点を配置し、信号点のそ
れぞれを1つの情報シンボルに対応させぞ伝送する多値
変復調通信方式が無線通信に用いられている。例えば、
信号点を正方形状に16個、64個、256個配置する
16値、64値。A multilevel modulation/demodulation communication system is used for wireless communication, in which a plurality of signal points are arranged on the phase plane of a modulated signal, and each signal point is transmitted in correspondence with one information symbol. for example,
16-value and 64-value, which arrange 16, 64, and 256 signal points in a square shape.
256値直交振幅変復調通信方式は、4ビツト。The 256-value orthogonal amplitude modulation and demodulation communication system uses 4 bits.
8ビツト、16ビツトの情報シンボルを1タイムスロツ
トで伝送できる。信号点の数が多(なるほど、1タイム
スロツトで伝送できる情報量は多くなり、電波の有効利
用をはかることができる。その代償として、信号点の数
が多くなるほど、伝送用ハードウェアや伝送路への特性
の要求も厳しくなる。8-bit or 16-bit information symbols can be transmitted in one time slot. The number of signal points is large (I see, the amount of information that can be transmitted in one time slot is large, and radio waves can be used effectively.In return, the larger the number of signal points, the more the transmission hardware and transmission path will need to be The requirements for characteristics will also become stricter.
さて、複数の位相面での信号点の組合せで1つの情報シ
ンボルを伝送するようにすれば、信号点の数の設定に自
由度が増す。そのため、電波の有効利用と伝送用ハード
ウェア等への要求の厳しさとの両立を図るべく信号点の
数を最適化するのに都合がよい。しかし、そのためには
、受信側で信号点の組合せの区切りを検出する、いいか
えれば、信号点の組合せの同期を確立する必要があざ。Now, if one information symbol is transmitted by a combination of signal points on a plurality of phase planes, the degree of freedom in setting the number of signal points increases. Therefore, it is convenient to optimize the number of signal points in order to achieve both effective use of radio waves and strict requirements for transmission hardware, etc. However, in order to do this, it is necessary to detect the separation of signal point combinations on the receiving side, or in other words, to establish synchronization of signal point combinations.
本発明の目的は、複数の位相面での信号点の組合せで1
つの情報シンボルを伝送し、受信側で信号点の組合せの
同期を容易に確立できる多値変復調通信方式を提供する
ことにある。The purpose of the present invention is to combine signal points on multiple phase planes into one
An object of the present invention is to provide a multilevel modulation/demodulation communication system that can transmit two information symbols and easily establish synchronization of a combination of signal points on the receiving side.
本発明の多値変復調通信方式は、変調信号の位相面にあ
らかじめ定めた複数の信号・点を配置し時間的に異なる
複数の前記位相面から1つずつ選択した前記信号点の組
合せを情報シンボルのそれぞれに対応させる多値変復調
通信方式において、送信側では前記情報シンボルに対応
させるべき前記信号点の組合せに用いる前記複数の位相
面の内あ−らかしめ定めた順番の位相面のみについて他
の前記位相面では用いることのない前記信号点を用い、
受信側では前記あらかじめ定めた順番の位相面を検出す
ることにより前記信号点の組合せの同期を確立する。゛
〔実施例〕
次に、本発明について図面を参照して説明すと。The multilevel modulation/demodulation communication system of the present invention arranges a plurality of predetermined signals/points on the phase plane of a modulated signal, and uses combinations of the signal points selected one by one from the plurality of temporally different phase planes as information symbols. In a multi-level modulation/demodulation communication system that corresponds to each of the above information symbols, on the transmitting side, only the phase planes in a predetermined order among the plurality of phase planes used for the combination of the signal points to correspond to the information symbols are Using the signal point that is not used in the phase plane,
On the receiving side, synchronization of the combination of signal points is established by detecting the phase planes in the predetermined order. [Example] Next, the present invention will be described with reference to the drawings.
第1図(a)及び(b)は本発明の一実施例を用いる通
信システムの送信側10及び受信側20を示すブロック
図である。FIGS. 1(a) and 1(b) are block diagrams illustrating a transmitting side 10 and a receiving side 20 of a communication system using one embodiment of the present invention.
本実施例で伝送される情報シンボルは9ビツトで表わせ
るシンボルであり、2’=512通りの状態をとる。こ
れら512通りの状態を第1及び第2の2つの位相面の
信号点の組合せに対応させる。The information symbol transmitted in this embodiment is a symbol that can be represented by 9 bits, and has 2'=512 states. These 512 states correspond to combinations of signal points of the first and second two phase planes.
第1位相面には、第2図(a)に示すように、24個の
信号点を配置する。又、第2位相面には、第2図(b)
に示すように、23個の信号点を配置する。第1位相面
の信号点を先に伝送し、続いて第2位相面の信号点を伝
送するように両位相面を順序付けすることにより、両位
相面の信号点の組合せは24X23=552通りとなる
。これら552通りの組合せのうち512を情報シンボ
ルの各状態と工対工に対応させる。As shown in FIG. 2(a), 24 signal points are arranged on the first phase plane. Also, in the second phase plane, as shown in Fig. 2(b)
As shown in the figure, 23 signal points are arranged. By ordering both phase planes so that the signal points of the first phase plane are transmitted first and then the signal points of the second phase plane, there are 24×23=552 combinations of signal points of both phase planes. Become. Of these 552 combinations, 512 are made to correspond to each state of the information symbol and engineering to engineering.
さて、伝送すべき情報シンボルの時系列は、9列のビッ
ト列D toとして、送信側10に入力すi。Now, the time series of information symbols to be transmitted is input to the transmitting side 10 as a nine-column bit string Dto.
ROM12は、ビット列10として入力した情報ビット
9ビツトのビットパターンを第2図(a)、(b)に示
す第1位相面、第2位相面のそれぞれ1つの信号点の組
合せに対応させるようにビット列りよ□、D□2を出力
する。第1位相面。The ROM 12 is configured to make the bit pattern of 9 information bits input as the bit string 10 correspond to a combination of one signal point each on the first phase plane and the second phase plane shown in FIGS. 2(a) and (b). Output the bit string □, D□2. First phase plane.
第2位相面の各信号点は64 (=2’ )値直交振幅
変調通信方式の信号点の一部になっているので、それぞ
れ6列のビット列D□□+I)t。によって各信号点を
表わすことにする。しかし、実際に用いる信号点は24
個又は23個であり、ビット列りユ8.D1□はそれぞ
れ約4.5列相当の情報量しか含まない。Since each signal point on the second phase plane is part of the signal points of the 64 (=2') value orthogonal amplitude modulation communication system, each of the six bit strings D□□+I)t. Let us represent each signal point by. However, the number of signal points actually used is 24.
or 23, and the bit string is 8. Each D1□ contains only an amount of information equivalent to about 4.5 columns.
並列直列変換回路13は、ビット列D1□l DI□の
1タイムスロツトの前半にビット列Dllを出力し、後
半にビット列D12を出力するようにビット列D□1.
D1□を6列のビット列に並列直列変換する。並列直列
変換回路13からのビット列を64値直交振幅変調用の
周知の変調器14に入力して変調信号Mを発生する。The parallel-serial conversion circuit 13 outputs the bit string Dll in the first half of one time slot of the bit string D1□lDI□, and outputs the bit string D12 in the second half of the bit string D1.
Parallel-serial conversion of D1□ into 6 bit strings. The bit string from the parallel-to-serial conversion circuit 13 is input to a well-known modulator 14 for 64-value orthogonal amplitude modulation to generate a modulation signal M.
変調信号Mは、伝送路を介して受信側20へ伝送される
。64値直交振幅変調信号用の周知の復調器21は、受
信した変調信号Mを復調し、復調出力信号である6列の
ビット列を一致判定回路22及び直列並列変換回路23
へ出力する。Modulated signal M is transmitted to receiving side 20 via a transmission path. A well-known demodulator 21 for a 64-value orthogonal amplitude modulation signal demodulates the received modulation signal M, and converts the 6 bit strings, which are demodulated output signals, to a coincidence determination circuit 22 and a serial-parallel conversion circuit 23.
Output to.
一致判定回路22は入力したビット列の連続した2タイ
ムスロツトのビットパターンの内いずれに第24番目の
信号点、すなわち、第1位相面にはあり第2位相面には
ない信号点に一致する信号点が発生しやすいかを判定し
、第24番目あ信号点を含むと判定したタイムスロット
に同期して同期パルスFを出力する。The coincidence determination circuit 22 detects a signal that matches the 24th signal point in the bit pattern of two consecutive time slots of the input bit string, that is, a signal point that is in the first phase plane but not in the second phase plane. It is determined whether the point is likely to occur, and a synchronization pulse F is output in synchronization with the time slot determined to include the 24th signal point.
直列並列変換回路23は、入力した6列のビット列を、
タイムスロットごとに交互に振分け、かつ、同期パルス
Fのタイミングではビット列D21に振向けるように直
列並列変換し、それぞれ6列のビット列D2□l D2
゜を出力する。このように同期パルスFを位相基準とし
て直列並列変換を行うことにより、ビット列D2□l
D2゜は、伝送誤りを無視すれば、送信側10における
ビット列D11゜Dl。と一致する。The serial-parallel conversion circuit 23 converts the input six bit strings into
The bit strings D2□l D2 are distributed alternately to each time slot, and serial-parallel conversion is performed so as to distribute them to the bit string D21 at the timing of the synchronization pulse F.
Outputs ゜. By performing serial-to-parallel conversion using the synchronizing pulse F as a phase reference in this way, the bit string D2□l
D2° is the bit string D11°Dl on the transmitting side 10, if transmission errors are ignored. matches.
ROM24は、送信側10でROM12が入力した9列
のビット列をビット列DIIIDI。に変換したのと逆
の変換で、ビット列D211D2゜を9列のビット列に
変換し、伝送誤りを無視すれば送信側10におけるビッ
ト列D 10に一致するビット列D 20を出力する。The ROM 24 converts the nine bit strings input by the ROM 12 on the transmitting side 10 into a bit string DIIIDI. The bit string D211D2.degree. is converted into a nine-column bit string by the inverse conversion to the bit string D211D2.degree., and if transmission errors are ignored, a bit string D20 that matches the bit string D10 on the transmitting side 10 is output.
直列並列変換回路23における同期パルスFの作用から
分るように、一致判定回路22で信号点の組合せの同期
が確立する。As can be seen from the action of the synchronization pulse F in the serial-parallel conversion circuit 23, synchronization of the combination of signal points is established in the coincidence determination circuit 22.
以上説明した実施例は、1つの情報シンボルを2つの位
相面で伝送し、各々に使用する信号点の数の差を1にし
たが、1つの情報シンボルを3つあるいはそれ以上の位
相面で伝送したり、各々に使用する信号点の数の差を2
あるいはそれ以上にする場合にも本発明を適用して同じ
効果を得ることができる。In the embodiment described above, one information symbol is transmitted in two phase planes, and the difference in the number of signal points used for each is set to 1, but one information symbol is transmitted in three or more phase planes. The difference in the number of signal points transmitted and used for each is 2
Alternatively, the present invention can be applied to obtain the same effect even when the number is greater than that.
以上説明したように本発明は、情報を伝送する為の複数
の位相面の内特定の位相面について特定の信号点を用い
ることにより、受信側でこの特定の信号点を検出するこ
とにより位相面の組合せの同期を確立するものであり、
受信側で簡単な回路で同期を確立することができる。As explained above, the present invention uses a specific signal point for a specific phase plane among a plurality of phase planes for transmitting information, and by detecting this specific signal point on the receiving side, the phase plane It establishes the synchronization of the combination of
Synchronization can be established on the receiving side with a simple circuit.
第1図(a)及び(b)は本発明の一実施例を用いる通
信システムの送信側10及び受信側20を示すブロック
図、第2図(a)及び(b)は本実施例における第1位
相面及び第2位相面での信号点配置を示す図である。
10・・・送信側、12.24・・・ROM、13・・
・並列直列変換回路、14・・・変調器、20・・・受
信側、21・・・復調器、22・・・一致判定回路、2
3・・・直列並列変換回路。FIGS. 1(a) and (b) are block diagrams showing a transmitting side 10 and a receiving side 20 of a communication system using an embodiment of the present invention, and FIGS. It is a figure which shows the signal point arrangement|positioning in a 1st phase plane and a 2nd phase plane. 10...Sending side, 12.24...ROM, 13...
- Parallel-serial conversion circuit, 14... Modulator, 20... Receiving side, 21... Demodulator, 22... Coincidence determination circuit, 2
3...Series-parallel conversion circuit.
Claims (1)
置し時間的に異なる複数の前記位相面から1つずつ選択
した前記信号点の組合せを情報シンボルのそれぞれに対
応させる多値変復調通信方式において、送信側では前記
情報シンボルに対応させるべき前記信号点の組合せに用
いる前記複数の位相面の内あらかじめ定めた順番の位相
面のみについて他の前記位相面では用いることのない前
記信号点を用い、受信側では前記あらかじめ定めた順番
の位相面を検出することにより前記信号点の組合せの同
期を確立することを特徴とする多値変復調通信方式。In a multilevel modulation/demodulation communication system in which a plurality of predetermined signal points are arranged on a phase plane of a modulated signal, and a combination of the signal points selected one by one from a plurality of temporally different phase planes corresponds to each information symbol. , on the transmitting side, the signal points that are not used in the other phase planes are used for only the phase planes in a predetermined order among the plurality of phase planes used for the combination of the signal points to correspond to the information symbols, A multilevel modulation/demodulation communication system, characterized in that, on the receiving side, synchronization of the combination of signal points is established by detecting the phase planes in the predetermined order.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2327955A JP2661363B2 (en) | 1990-11-28 | 1990-11-28 | Multi-level modulation / demodulation communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2327955A JP2661363B2 (en) | 1990-11-28 | 1990-11-28 | Multi-level modulation / demodulation communication system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH04196944A true JPH04196944A (en) | 1992-07-16 |
JP2661363B2 JP2661363B2 (en) | 1997-10-08 |
Family
ID=18204884
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2327955A Expired - Fee Related JP2661363B2 (en) | 1990-11-28 | 1990-11-28 | Multi-level modulation / demodulation communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2661363B2 (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6367851A (en) * | 1986-09-09 | 1988-03-26 | Fujitsu Ltd | Transmission system for frame synchronizing signal |
-
1990
- 1990-11-28 JP JP2327955A patent/JP2661363B2/en not_active Expired - Fee Related
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6367851A (en) * | 1986-09-09 | 1988-03-26 | Fujitsu Ltd | Transmission system for frame synchronizing signal |
Also Published As
Publication number | Publication date |
---|---|
JP2661363B2 (en) | 1997-10-08 |
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