WO1986000186A1

WO1986000186A1 - Circuit for demodulating phase shift keyed signals

Info

Publication number: WO1986000186A1
Application number: PCT/GB1985/000252
Authority: WO
Inventors: Duncan Keith Wilson Hopkins
Original assignee: Independent Broadcasting Authority
Priority date: 1984-06-08
Filing date: 1985-06-10
Publication date: 1986-01-03
Also published as: EP0182850A1; GB8414623D0

Abstract

A demodulator network adds a phase control feedback loop including an automatic phase control amplifier (28) and voltage controlled phase shifter (27) to the normal demodulator (20) and delay circuit (26) configuration whereby to control the demodulator (20) in response to detection of its own output. In a further embodiment, two differently phase shifted signals can be demodulated using the same control feedback loop by adding a further demodulator in parallel with the demodulator (20) and adding a phase shift circuit into the feedback loop.

Description

CIRCUIT FOR DEMODULATING PHASE SHIFT KEYED SIGNALS

The present invention relates to the demodulation of differential phase shift keyed signals.

It is known to modulate digital data for trans¬ mission purposes using phase shift keying (PSK) and in direct broadcasting by satellite it has been proposed to modulate the digital data burst contained in the signal representing an active line of television using 2-4PSK (also known as symmetrical phase shift keying) . The basic techniques for demodulating such phase shift keyed signals using a so-called differen ial demodulator are well establish and reported widely in the literature. However, certain performance degradations can arise in such differential demodulators. The present invention provides a circuit for demodulating differential phase shift keyed modulated signals comprising a feedback circuit connected across a demodulator, the feedback circuit including an automatic frequency control amplifier responsive to demodulated signals for producing control information to which the demodulator is responsive.

An advantage of this circuit is that it provides automatic correction of the performance degradations which occur in differential demodulators. The circuit is also capable of being adapted for use with other phase shift keyed signals such as binary phase shift keyed signals. The technique is applicable to any bit rate e.g. 20.25 M bits/sec.

Features and advantages of the present invention will become apparent from the following description of embodiments thereof given by way of example with reference to the accompanying drawings, in which: -

Figure 1 shows a block diagram representing a DBS receiver; Figure 2 shows a block diagram of a PSK demodulator according to the present invention; and

Figure 3 shows a block diagram of a further form of PSK demodulator according to the present invention.

Before describing the demdoulator circuit of the present invention in detail it is thought helpful if one specific application of such a circuit were to be described. Attention is therefore directed to Figure 1 which. shows one example of a direct broadcast by satellite receiver in block diagram form. It is to be assumed that the signal received by a dish aerial 10 is in the form of television line signals each of which contains a phase shift keyed digital portion and a multiplexed analogue component portion. In this example, 2-4 PSK is used for modulating the digital portion of the signal but it is to be understood that this is but one example of a PSK signal which can be demodulated using the present invention.

After reception by the dish aerial 10, the signal is down-converted in first and second converter circuits 11 and 12 to produce a suitable IF signal for subsequent demodulation. The output from the down-converter 12 is fed to a PSK demodulator network indicated in broken lines by the reference numeral 14 and is also fed to a vision demodulator network which is this case is based on an FM demodulator. The vision demodulator network is indicated in broken lines by the reference numeral 15- Since the latter demodulator network 15 is not the subject of the present invention it will not be described further and attention is now directed to the PSK demodulator network 14- The network 14 is based on a differential demodulator which is most conveniently in the form of a multiplier 20. The input PSK signal is fed through a symbol shaping filter 21 prior to reception by the multi¬ plier 20 so that the pulse shape and thermal noise spectrum at the multiplier inputs may be defined and the filter has a bandwidth approximately equal to the transmission bit rate.

The regenerated output from the multiplier 20 con¬ stitutes the digital data output. In this particular example, the data contains information relating to line and frame syncs for the broadcast signal and hence a sync detection circuit 22 is connected to the output of the de¬ modulator 20 and line and frame sync signals are output from the detector circuit .

Turning now to Figure 2, this shows more detail how the PSK demodulator network 14 excepting circuit 22 maybe constructed and the same reference numerals are used for the same parts.

It will be noted that it is preferred to add a limiter circuit 25 at the output of the filter 21 before the multiplier 20. The limiter is a hard limiter which changes the shape of the demodulated "eye" at the symbol sampling instants. The error producing conditions at the output of the multiplier 20 are the same as if no limiter were present and hence the limiter can often be dispensed with in basic differential demodulators. The limiter 25 does not fundamentally change the BER. The output of the limiter 25 is fed to a multiplier and also to a delay line which delays the signal output from the limiter 25 by a period Tl which is equal to the inverse of the bit rate of the input signal. In previously proposed differential demodulators the output of the delay circuit 26 would be fed directly to the multiplier 20 but in this embodiment the output of the delay circuit 26 is fed to a voltage controlled phase shifter 27 which is controlled by a control voltage generated from an automatic frequency control amplifier 2δ having an input connected to the output of the multiplier 20. In this case, a low pass filter 29 is interposed between the output of the multiplier 20 and the input of the loop amplifier 28, which filter 29 is arranged to reject components at two times the inter¬ mediate frequency. The output of the filter 29 is also fed to a clock extraction and regenerator circuit 30 whose output is the demodulated data signal. While the limiter 25 is not necessary for use in previously proposed differential PSK demodulators, it has been found advantageous to insert such a device in view of the^* fact that it has ■an effect on the performance of the clock recovery system and the automatic phase control feedback loop.

The demodulator network shown in Figure 2 has certain optimum IF frequencies, where the demodulation requirements for exactly one symbol delay and 90° phase shift are both satisfied. However, only a very small degradation in demodulation performance (dependent upon the exact details of the demodulator but probably no larger than O.ldB) results if we use a non optimum IF frequency, but change the delay line length very slightly from its nominal one symbol delay, to obtain the correct phase shift conditions.

Therefore there is no practical restriction on the exact IF frequency provided the absolute frequency is high enough that the resultant delay modification is small compared to one symbol period. Input Frequency Errors

The effects of frequency errors at the input to the differential demodulator network shown in Figure 2 will cause degradation to the noise performance of the 2-4PSK differential demodulator. This is due to:- 1. Intersymbol interference (ISI) since the signal is no longer centred in the symbol shaping filter passband; 2. Phase errors at the delay line output. Phase errors should be less than 'a few' degrees. For a delay line at length T seconds, the phase shift is 0 = 27rfT radians. Thus for a signal frequency error f"c Hz, the phase error ^ 0 = l lf T <? f radians. Clearly the phase error depends only upon the frequency error **? f , independent of the absolute IF frequency. For example for C-MAC 2-4PSK data, with T = 49.4ns, for a 1 MHz frequency error the phase error is 17.6°, which is estimated to cause a O.SdB C/N ratio degradation at 10~³ BER in the absence of ISI.

The C/N ratio degradation due to these effects combined depends upon the particular symbol shaping filter used. As an example for a demodulator using a 4th order 21 MHz bandwidth Butterworth input filter, we have measured a ldB C/N ratio degradation at 10 BER for 1 MHz frequency error. Delay Line Time Errors

The effect of delay line time errors in the nominal 1 symbol delay line shown in Figure 2 is also to cause phase errors at the multiplier input. In this case the phase error o 0 = 27r f <P Υ , therefore the phase error is proportional to the IF frequency. As an example at 1 % time error with demodulator input carrier frequency of 150 MHz results in a phase error of 27°- which will casuse approximately l.SdB C/N ratio degradation at 10 BER. To eliminate the effects of IF frequency errors, and delay line errors Automatic Phase Control (APC) is used to maintain 'optimum' demodulation performance. Control input to the APC loop is derived from the demodulator output itself. When data pattern noise has been removed by a low pass filter, the remaining average value gives a phase detector characteristic of the form sin 2^*WfTl, where Tl is the delay line delay. This control voltage from the amplifier 2δ can be used either to control a voltage controlled phase shifter, as shown in Figure 2, alternatively the demodulator input frequency can be changed such that the phase shift is correct, and thereby maintain optimum demodulation conditions. In the latter case, if the symbol shaping filter 21 is within the loop, such frequency errors will give rise to C/N ratio degradation due to the signal no longer being centred in the symbol shaping filter passband; therefore the phase shift method is preferred.

For direct broadcasting by satellite using C-MAC, the burst nature of the 2-4PSK signal means that the APC Loop must be gated at the line rate. Therefore APC can not operate until line sychronisation has been acquired. An alternative differential demodulator network with APC is shown in Figure 3- this network shares many identical parts with the network described in relation to Figure 2 and hence the same reference numerals will be used for the same parts. In Figure 3_. the points A and B represent alternative inputs to the low pass filter 29j which are used dependent upon the actual carrier frequency at the 2-4PSK differential demodulator input .

Connection A would be used for IF frequencies f = —-r=-τ— HZ (Tl is the delay line delay, nominally equal to l/Bit rate) and connection B for IF frequencies

HZ where n is an integer. Thus the demodulated data is obtained by processing signals on either A or B.

It will be noted that the network shown in Figure 3 5 has many similarities to the network shown in Figure 2 but in this case the output from the limiter 25 is fed to the voltage controlled phase shifter 27 and the output of the phase shifter 27 is then fed to the delay line 26 which is directly connected to the multiplier

10 20. Further, a multiplier 31 receives as one input the output from the limiter 25 but also a phase shifted output from the delay line 26 through a phase shifter 33 - The output of the multiplier 31 is connected to a further multiplier 33 and, if the IF frequency so dictates to

15 connection B of the filter 29- The multiplier 33 also receives the output from the multiplier 20 which output is fed to the connection A of the lowpass filter 29 •

The output of the multiplier 32 then forms the input to the amplifier 2S. 2_Q Degradation to the demodulation performance occurs due to the phase errors described above. This may be corrected by introducing a phase shift using the phase shifter 27.

Control for the phase shifter is obtained by

2 multiplying together the outputs A and B and low pass filtering amplifying in the loop amplifier 28. By this means, delay line errors are dynamically corrected, the control signals being obtained from the processed

2-4PSK modulation to maintain 'optimum' demodulation j „0- conditions.

Thus the effects of both delay line and input frequency errors are simultaneously minimised.

For both the demodulator network described in Figure 2 and 3- the phase shifter 27 may be dispensed -r with, and a frequency converter and low pass filter introduced immediately following the symbol shaping filter 21. The output frequency of this converter is controlled by the same control voltage signal in such a way as to maintain 'optimum' demodulation conditions. The output frequency of the converter is chosen to be either ⁿ .* HZ or ^■*-—— HZ as appropriate.

For both the networks described, the control voltage obtained for driving the voltage controlled phase shifter (or frequency converter) is dependent upon the exact parameters of the phase shift keyed input signal, on the specific symbol shaping filter used at the demodulator input, and is dependent on whether the limiter following the symbol shaping filter 21 as shown in Figures 2 and 3 is used. Although a 2-4PSK demodulator has been described, similar techniques can be applied to a binary PSK demodulator.

Claims

CLAIMS :

1. A demodulator network for demodulating differential frequency shifted keyed modulated signals comprising a demodulator (20) having an input for modulated signals and an output connected to a filter (29), and a delay circuit (26) connected to the demodulator (20) for supplying delayed input modulated signals characterised in that a feedback loop (27,28) is provided connected between the output of the demodulator (20) and the further input thereto for supplying controlled delayed signals to the demodulator (20) whereby to correct errors in demodulation.

2. A network according to claim 1, wherein the feedback loop comprises an automatic phase, control amplifier (28) having an input connected to the output of the demodulator (20) and an ouput connected to a controlled circuit (27) for controlling the delayed signals fed to the demodulator (20).

3 - A network according to claim 2, wherein the controlled circuit is a phase shifter circuit (27)-

4- A network according to claim 2, wherein the controlled circuit is a frequency converter.

5. A network according to any one of claims 2,3 or 4, wherein the delay circuit (26) is between the input for modulated signals and the controlled circuit (27)-

6. A network according to any one of claims 2, 3 or 4, wherein the delay circuit (26) is connected between the output of the controlled circuit (27) and the further input to the demodulator (20).

7. A network according to claim 6 , wherein a further demodulator (31) is provided, one input of which is conn¬ ected to the input for modulated signals and another input of which is connected to the delay circuit (26) via a phase shift network (32), the amplifier (28) being connected to the outputs of both demodulators (20,31) via a multiplier circuit (32).

8. A network according to claim 7- wherein the filter 28 is provided with two inputs, one connected to the output of the first-mentioned demodulator (20) and the other to the further demodulator (31)-