JP2654535B2 - Reset method for automatic equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reset system for an automatic equalizer for compensating for equalization of a digital multilevel modulated signal subjected to transmission distortion in a receiving apparatus of a digital radio communication system, and more particularly to a multipath fading propagation path. The present invention relates to a reset method for an automatic equalizer suitable for compensating for intersymbol interference of a digital multilevel modulation signal that has passed through the above.

[0002]

2. Description of the Related Art A conventional reset system for an automatic equalizer of this type is disclosed in Japanese Patent Laid-Open Publication No. 3-3426. The automatic equalizer in this demodulator compensates for inter-symbol interference by equalizing the in-phase and quadrature-side digital signals supplied from the demodulation circuit that performs synchronous detection with a transversal type automatic equalization circuit. , To generate an in-phase and quadrature-side data signal that compensates for this intersymbol interference. These data signals are further frame-synchronized by the reception code processing circuit, converted into a data signal of the same signal format as the data signal in a row input on the transmission side of the wireless communication system, and output. . At this time,
If the reception signal processing circuit has a configuration in which frame synchronization is performed with a single input data signal sequence, an error or an alarm cannot be determined because a parity check bit can be monitored only after frame synchronization. Therefore, even if the control signal of either the in-phase or quadrature-side automatic equalizer diverges, if the carrier synchronization of the demodulator is established, an alarm can be detected only after frame synchronization has been established.

[0003] For this reason, the reset method of the automatic equalizer proposed in the above-mentioned patent publication takes a frame configuration in units of in-phase and quadrature signal trains on the transmission side, and the in-phase and quadrature side on the demodulation device side. Establishes frame synchronization independently for each data signal, and when any one of the frame synchronization is lost, returns the tap coefficient of the automatic equalization circuit of the corresponding signal sequence to the initial value and performs the compensation operation. Is resetting to stop.

Another conventional reset method for an automatic equalizer is disclosed in Japanese Patent Laid-Open Publication No. 4-35442. The automatic equalizer in the demodulator measures the sign-error rate of the data signal outputted from the automatic equalizer, intermittently resetting the automatic equalizer exceeds a predetermined value there is the Bit Error Rate Is described.
However, this automatic equalizer does not reset the equalizing circuit independently for each of the in-phase and quadrature, and therefore the prior art described in the above-mentioned Japanese Patent Laid-Open Publication No. 3-3426. In order to solve this problem, it is necessary to form a frame independently for each of the in-phase data signal and the quadrature data signal.

[0005] Also, the use of a coded modulation scheme capable of increasing the system gain over the conventional multi-level modulation scheme is described in the literature (S. Maeda, E. Sasaki, A. Ush).
irokawa and Y. Koizumi, "Ad
advanced SDH radio systems
for transport STM-1 ", Radi
o Relay Systems, 11-14 Oct
over 1993, conference Publ
ication NO. 386, IEEE, 1993,
pp 349-pp 354).

FIG. 5 is a block diagram showing a transmitting apparatus and a receiving apparatus applied to the coded modulation system.

The transmitting apparatus encodes input data S110a composed of a plurality of signal strings by a transmission code processing circuit 110, and converts the encoded input data S110a to a modulation circuit 120.
Performs digital multi-level modulation to generate an encoded modulation signal S1b,
This signal S1b is output to the propagation path. Further, the receiving apparatus demodulates the coded modulation signal S1a in the same signal format as the coded modulation signal S1b received from the propagation path into a baseband signal by the demodulation circuit 10, and converts this signal to the automatic equalization circuit 2.
The equalization is compensated by 0, and the reception code processing circuit 30 reproduces the output data S110b in the same signal format as the input data S110a from the equalized compensation signal.

[0008] Here, the transmission code processing circuit 110 arranges each signal sequence of the input data S110a at an optimum signal point. For this reason, the processing circuit 110 needs to adopt a frame configuration in the serial conversion circuit 113 in the preceding stage of the encoding circuit 114, and needs to perform a decoding process using the output of the automatic equalization circuit 20 on the receiving device side. is there. In other words, the reception code processing circuit 30 does not have the concept of the data signal on the in-phase side and the quadrature side.
The conventional automatic equalizer reset method, which required frame synchronization for each orthogonal signal sequence, cannot be applied as the automatic equalizer reset method used for the coded modulation method.

[0009]

In the conventional reset method of the automatic equalizer described above, it is necessary to establish frame synchronization independently for each of the in-phase and quadrature-side data signals from the automatic equalizer circuit. It is necessary to adopt a frame structure for each data signal sequence supplied to the modulation circuit, not for the data signal sequence input to the transmission device. That is, the conventional reset method of the automatic equalizer has a disadvantage that the degree of freedom in selecting the frame configuration is low.

Further, in the conventional reset method of the automatic equalizer, it is necessary to synchronize the frame of each of the in-phase and quadrature-side data signals independently. Therefore, the reception code processing circuit connected to the above-mentioned automatic equalizer circuit However, there is a disadvantage that the circuit configuration becomes complicated.

Further, the conventional reset method of the automatic equalizer has a drawback that it cannot be applied to a wireless communication system using a modulation method having no concept of in-phase and quadrature such as a coded modulation method.

[0012]

According to the reset method of the automatic equalizer of the present invention, a digital multi-level modulation signal is synchronously detected to convert an in-phase baseband signal and a quadrature baseband signal orthogonal to the in-phase baseband signal. A resulting demodulation circuit, a first analog-to-digital conversion circuit for converting the in-phase baseband signal to a first digital signal, and a second analog-to-digital conversion for converting the quadrature baseband signal to a second digital signal A circuit that receives the first digital signal and the second digital signal and generates an in-phase data signal and a quadrature data signal, each of which compensates for inter-symbol interference between the first digital signal and the second digital signal, respectively. The automatic equalizing means and the first reset signal and the second reset signal respectively responding to the reset signal corresponding to the reset signal. An automatic equalizing circuit having reset means for resetting dynamic equalizing means, respectively, and a first error pulse receiving the in-phase baseband signal and generating a first error pulse corresponding to waveform deterioration of the in-phase baseband signal A generator, a first identification circuit for generating the first reset signal when the number of the first error pulses exceeds a predetermined first threshold value within a predetermined period, and receiving the quadrature baseband signal. A second error pulse generator for generating a second error pulse corresponding to the waveform deterioration of the quadrature baseband signal, and when the number of the second error pulses exceeds a predetermined second threshold value within a predetermined period. A second identification circuit for generating the second reset signal.

The automatic equalizer reset method employs a configuration in which each of the first and second error pulse generators respectively generates the error pulse corresponding to the convergence point spread of the baseband signal. be able to.

Each of the error pulse generators is
A full-wave rectifier circuit for full-wave rectifying the baseband signal;
It is possible to adopt a configuration including a flip-flop circuit that outputs a predetermined logical value each time the level of the full-wave rectified baseband signal exceeds a predetermined threshold.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

This automatic equalizer is used for a receiving device in a digital radio communication system, and receives a received digital multilevel modulation signal S1 at an input terminal 101 of a demodulation circuit 1. The received digital multi-level modulation signal S1 is added to a data signal (main signal) input on the transmission apparatus side of this system by a DSC (Digital Service Ch) for a meeting signal.
(multiple-level modulation signal) in which an (annel) signal, a WS (way side) signal, a switching control signal, a frame synchronization bit for determining a radio frame, and the like (auxiliary signal) are multiplexed. I have. The received digital multilevel modulation signal S1 generally suffers from waveform deterioration due to multi-path fading that occurs in a propagation path, and causes intersymbol interference.

The demodulation circuit 1 synchronously detects the received digital multi-level modulation signal S1 and delays the in- phase baseband signal S _2P and the reproduced carrier signal S12 by 90 ° in phase with the reproduced carrier signal S12. It was recovered carrier signal S
A quadrature baseband signal S _2Q synchronously detected at _12Q is generated. The in-phase baseband signal S _2P is converted into a digital signal S _3P identified and reproduced by an analog / digital conversion circuit (A / D) 4. Similarly, the quadrature baseband signal S _2Q is converted into a digital signal S _3Q by an analog / digital conversion circuit (A / D) 5. Digital signals S _3P and S
_3Q is supplied to a transversal type automatic equalizing circuit 2.

The automatic equalization circuit 2 performs a waveform equalization of the digital signal S _3P by the transversal equalization circuit 21 to generate an in-phase data signal S _{6P in} which the intersymbol interference of the signal S _3P is compensated. The waveform of the digital signal S _3Q is equalized by the conversion circuit 22 to generate an orthogonal data signal S _{6Q in} which the intersymbol interference of the signal S _3Q is compensated. Also,
When the automatic equalization circuit 2 receives the reset signal _S5P ,
The reset operation for setting the tap coefficient of the transversal equalization circuit 21 to the initial value is performed. When the reset signal _S5Q is received, the reset operation for setting the tap coefficient of the transversal equalization circuit 22 to the initial value is performed.

[0020] aforementioned reset is performed, the automatic equalizing circuit 2 stops compensation operation of intersymbol interference for the digital signal S _3-Way and S _3Q, the digital signal S _3-Way and S _3Q not subjected to waveform equalization (S25) is supplied to the decision circuits 205 of the transversal equalization circuits 21 and 22, and the outputs of these decision circuits 205 are output as the in-phase data signal S _6P and the quadrature data signal S _6Q . The automatic equalizer circuit 2, the phase control signal generating circuit 23 using well known techniques, to generate a phase control signal S7 from the in-phase digital signal S 25 and quadrature digital signal S27, the demodulation circuit 1 by the phase control signal S7 Built-in voltage controlled oscillator 10
5 controls the frequency of the reproduced carrier signal S12 generated.

The in-phase data signal S _6P and the quadrature data signal S _6Q are supplied to the reception code processing circuit 3. The code processing circuit 3 synchronizes the in-phase data signal S _6P and the quadrature data signal S _{6Q with} a frame, and separates the frame-synchronized signal S _6P and the signal S _6Q into the main signal and the auxiliary signal. Output to external circuit.

Next, a reset method which is a feature of the present invention will be described.

In-phase baseband signal S from demodulation circuit 1
_2P is also supplied to an error pulse generator (EPG) 6. The error pulse generator 6 generates a number of error pulses S _4P corresponding to the waveform deterioration of the in-phase baseband signal S _2P due to the addition of noise and the deterioration of the transmission characteristics of the propagation path. Error pulse generator 6, as will be described later with reference to FIGS. 2 and 3, using the error pulse generation technique using spread convergence point of the eye pattern of the in-phase baseband signal S _2P. The error pulse _S4P is supplied to the identification circuit 8. When the number of error pulses S _4P exceeds a predetermined threshold value within a predetermined period, the identification circuit 8 outputs the reset signal S on the in-phase side.
_{Generates 5P} . This reset signal S _5P is, as described above,
The transversal equalization circuit 21 of the automatic equalization circuit 2 is reset, and the operation of equalizing the waveform of the digital signal _3P in the transversal equalization circuit 21, that is, the operation of compensating for intersymbol interference is stopped.

As described above, the error pulse generator (EP
G) 7 is a quadrature baseband signal S _2Q from the demodulation circuit 1
Then, the number of error pulses S _4Q corresponding to the waveform deterioration of the signal S _2Q is generated. The error pulse S _4Q is sent to the identification circuit 9
When the number of error pulses S _4Q exceeds a predetermined threshold within a predetermined period, the identification circuit 9 generates a reset signal S _5Q on the orthogonal side. The reset signal _S5P resets the transversal equalization circuit 22 of the automatic equalization circuit 2 and stops the waveform equalization operation of the digital signal _3Q in the transversal equalization circuit 22, that is, the operation of compensating for intersymbol interference.

As described above, this automatic equalizer reset method uses the in-phase baseband signal S _2P and the quadrature baseband signal S _2Q from the demodulation circuit 1 connected before the automatic equalizer circuit 2. The transversal equalization circuit 21 as the in-phase waveform equalization circuit and the transversal equalization circuit 22 as the quadrature waveform equalization circuit can be reset independently. Conversely, the resetting method of the automatic equalizer uses a transversal method without extracting two in-phase and quadrature frame synchronous / asynchronous signals by the reception code processing circuit 3 connected to the subsequent stage of the automatic equalizer 2. Equalization circuit 2
1 and 22 can be reset independently.

Next, the demodulation circuit 1 of the automatic equalizer of the present embodiment.
Will be described in detail. The received digital multilevel modulation signal S1 received by the input terminal 101 is 16 QAM (Quadrature Ampli) for simplicity of explanation.
Tude Modulation) signal. The received digital multi-level modulation signal S1 is divided into two by a distribution circuit (H) 102, and one of the digital multi-level modulation signals S _11P
Is supplied to the multiplication circuit 103 by the other digital multilevel modulation signal S.
_11Q is supplied to the multiplication circuit 104. On the other hand, the voltage controlled oscillator 105 receives the phase control signal S7 from the automatic equalizing circuit 2, and generates a reproduced carrier signal S12 that is phase-synchronized with the received digital multilevel modulation signal S1. One of the reproduced carrier signals S12 is supplied to a multiplying circuit 103, and the other is a reproduced carrier signal _S12Q whose phase is delayed by π / 2 by a π / 2 phase shift circuit 106, and is supplied to a multiplying circuit 104. Supplied. Therefore, the multiplying circuits 103 and 104 synchronously detect the digital multilevel modulation signals S _11P and S _11Q , the multiplying circuit 103 detects the in-phase baseband signal S _13P , and the multiplying circuit 104 detects the quadrature-side baseband signal S _{11P. Produces 13Q} .

The baseband signals S _13P and S _13Q are
The harmonic components are removed by the low-pass filters 107 and 108, respectively, to obtain an in-phase baseband signal _S2P and a quadrature baseband signal _S2Q .

The transversal equalization circuit 21 built in the automatic equalization circuit 2 will be described in detail. The transversal equalization circuit 21 includes a tap control circuit 201, tap delay lines 202 and 203, an adder 204 This is a 7-tap transversal equalization circuit including a determination circuit 205. The tapped delay line 202 has six stages of delay circuits for delaying the clock cycle of the digital signal _S3P , and the delay signals S23 (R _-3 , R _{-2) of the} corresponding time slots from each of the delay circuits. , ..., R ₀ , ..., R
₊₂ , R _{+ 3} ). The tap control circuit 201 controls each tap coefficient of the tapped delay line 202 by the tap coefficient control signal S22. Each (R _-3 ,
R ₋₂ ,..., R ₀ ,..., R ₊₂ , R ₊₃ ) are weighted by these tap coefficients and further added by the adder 204 to become an addition signal S25, which is obtained from the digital signal from the in-phase side. Intersymbol interference is compensated.

Similarly, the tapped delay line 203 includes six stages of delay circuits for delaying the clock period of the digital signal S _3Q by the input signal and the delay of the corresponding time slot from each of the delay circuits. The signal S24 (I _-3 ,...,
I ₋₁ , I ₊₁ ,..., I ₊₃ ). Tap control circuit 20
1 controls each tap coefficient of the tapped delay line 203 by the tap coefficient control signal S21, and outputs the delay signal S24
(I _-3 ,..., I _-1 , I ₊₁ ,..., I ₊₃ ) are weighted. The weighted delay signal S24 is added to the weighted delay signal S23 by the adder 204, and intersymbol interference from the orthogonal digital signal is compensated.

The determination circuit 205 outputs the upper two bits of the addition signal S25 to the reception code processing circuit 3 as the in-phase data signal _S6P , and outputs the third bit to the tap control circuit 201 as the error signal S26. Also, the tap control circuit 201
Is the MS of the in-phase digital signal S _3P during waveform equalization.
A tap coefficient control signal S22 for determining a tap coefficient of the tapped delay line 202 is generated based on the representation signal S28, which is a B (Most Significant Bit) signal, and the error signal S26.

Here, when the reset signal S _5P is supplied to the tap control circuit 201, the tap control circuit 201 sets only the tap coefficient control signal of R ₀ of the delay signal S23 to “1”.
This generates tap coefficient control signals S21 and S22 in which the other tap coefficient control signals are "0". Therefore, the addition signal S25 is a signal obtained by delaying the input digital signal _S3P by two clock cycles, and the transversal equalization circuit 21
Means that the compensation operation has been stopped. This also means that each of the tap coefficient control signals S21 is in an initial value state, that is, the transversal equalization circuit 21 is in a reset state. That is, when the reset signal _S5P is supplied to the tap control circuit 201, the transversal equalization circuit 21 is reset.

The transversal equalization circuit 22 for equalizing the waveform of the digital signal S _3Q on the orthogonal side also performs the same waveform equalization and reset operation as the traversal equalization circuit 21.
That is, the transversal equalization circuit 22 receives the digital signal S _3P on the in-phase side, the digital signal S _3Q on the quadrature side, and the tap control signal S22, and performs a waveform equalizing operation using the above-described delay line with tap and the tap control circuit. Do
Upon receiving the reset signal _S5Q , the digital signal S on the orthogonal side
A reset operation for outputting a signal _S6Q obtained by delaying _3Q by two clock cycles is performed.

FIG. 2 is a block diagram of the error pulse generator 6 used in the automatic equalizer of this embodiment. Also, FIG.
FIG. 8 is an explanatory diagram of the operation of the error pulse generator 6, (a) an eye pattern of the in-phase baseband signal S _2P , (b) a signal waveform of the full-wave rectified signal S 61 when no noise is added,
(C) is a signal waveform of the full-wave rectified signal S61 when noise is added.

Referring to FIGS. 2 and 3 together, the in-phase baseband signal S _2P supplied to the error pulse generator 6 is shown.
Since the received digital multilevel modulation signal S1 is a 16 QAM signal, the optimal sampling time Ts is 4 (16
= 4 ² ) convergence points, that is, (+2), (+1), (−
It has convergence point levels of 1) and (-2) (FIG. 3 (a)
reference). The full-wave rectifier circuit 61 outputs the in-phase baseband signal S
_2P is full-wave rectified to generate a full-wave rectified signal S61.

If there is no waveform deterioration due to noise or distortion in the in-phase baseband signal S _2P , the level (+2) and (−)
2) Since the absolute amplitude values of (+1) and (-1) are equal, the convergence points of the full-wave rectified signal S61 are (+2) and (+1).
(See FIG. 3B).

The flip-flop circuit (F / F) 62 reads the full-wave rectified signal S61 at the optimum sampling time Ts. The circuit 62 sets the level threshold (threshold level) for the full-wave rectified signal S61 to the A level higher than the (+2) level by the Y level, and when there is no waveform deterioration due to noise or distortion, the output signal The "0" level is output to S62. Therefore, the logical product (AN
D) The output of the circuit 63 is prohibited.

On the other hand, if there is waveform deterioration due to noise or distortion, each convergence point of the full-wave rectified signal S61 shows a spread (see FIG. 3C), so that there is a level higher than the A level at the optimal sampling time Ts. . Therefore, the output signal S62 at that time becomes "1" level. Accordingly, the error pulse S _4P synchronized with the clock signal S63 to the output of the logical product (AND) circuit 63 At a this point appears.

In the present embodiment, the error pulse generator 6 sets the input signal threshold level of the flip-flop circuit 62 higher than the (+2) level. can get. In this case, the output S62 of the flip-flop circuit 62 is a logical value at a normal time, that is, when there is no noise addition.
In order to take 1 ", a logical sum (O) is used instead of the AND circuit 63.
R) Use a circuit.

The probability (time ratio) that the clock signal S63 appears in the above-mentioned error pulse signal _S4P increases as the waveform distortion or noise addition of the received digital multilevel modulation signal S1 increases. The clock signal S63 is extracted using the in-phase baseband signal _S2P or the quadrature baseband signal _S2Q using a known technique.

FIG. 4 is a block diagram of the identification circuit 7 used in this embodiment.

The counter 81 of the identification circuit 7 counts the error pulses S _4P supplied from the error pulse generator 6 and counts a predetermined number N (N is an integer) of error pulses S _4P. The counter output signal S81 of "1" is output. On the other hand, the counter 82 counts the clock signal S43 and determines a predetermined M (M is an integer) clock signals S4
When 3 counting, Cau te output signal S8 of the logical value "1"
2 is output. In addition, RS (Reset Set ty)
pe) The flip-flop 83 outputs the counter output signal S8
When 1 is a logical value "1", the reset signal S of the logical value "1"
_When the counter output signal S82 has the logical value "1", the reset signal _S5P having the logical value "0" is output. That is,
N error pulses within a certain period specified by M
When this occurs, the counter output signal S81 changes to the counter output signal.
Since it becomes "1" before the signal S82 , the reset signal _S5P on the in-phase side becomes a logical value "1". Conversely, an error occurs during the M period.
-In normal operation when only N pulses or less are generated,
Data output signal S82 is earlier than counter output signal S81.
1 ”, the reset signal S _5P on the in-phase side is a logical value“
0 ".

The number of error pulses S _4P is an amount proportional to the error of the main signal (in-phase baseband signal S _2P ), and N / M is M because the clock signal S43 sets a certain time. This is proportional to the degradation threshold (threshold) of the code error rate of the main signal during the period . Therefore, the relationship between the code error rate and the number of error pulses S _4P is determined in advance, and the relationship corresponds to the code error rate deterioration threshold value.
By setting the value of N / M, the code error rate of the main signal becomes worse than a certain set value and the error
When the number of _{switches S4P} exceeds N, the identification circuit 8 outputs a reset signal _S5P . This bit error rate is set to be approximately equal to the value of normal frame asynchronous detection, that is, approximately 10 ⁻² to 10 ⁻³ . Of course, this set value is a value to be set according to the system request value.

The configurations of the error pulse generator 7 and the identification circuit 9 are the same as the configurations of the error pulse generator 6 and the identification circuit 8, respectively, and the description is omitted.

Although the error pulse generators 6 and 7 and the identification circuits 8 and 9 in this embodiment have been described assuming that the received digital multilevel modulation signal S1 is a 16QAM signal,
Generally, the above-described operation can be realized with the same configuration even in the case of a 2 ²ⁿ (n is a positive integer) QAM signal.

That is, the number of convergence points of the in-phase baseband signal S _2P shown in FIG. 3 is 2n ((−n) levels, (−
(N-1) level, ..., (-1) level, (+1) level
,..., (N-1) level, (n) level), and the same function is realized by setting the input signal threshold of the flip-flop 62 higher than the (+ n) level.

[0046]

As described above, according to the present invention, the degree of waveform deterioration of the in-phase and quadrature baseband signals from the demodulation circuit is counted into the number of error pulses, and the number of error pulses is set to a predetermined threshold value. If it exceeds, the automatic equalizing circuit is reset. Therefore, the present invention does not require independent frame synchronization for each of the in-phase and quadrature data signals from the automatic equalizing circuit for this reset. This has the effect of increasing the degree of freedom in selecting the frame configuration of the signal and simplifying the circuit configuration of the reception code processing circuit connected downstream of the automatic equalizer.

Further, even if the digital multi-level modulation signal is a signal of a modulation system having no concept such as in-phase and quadrature components after decoding such as a coded modulation system, the signal is decoded on the in-phase side and the quadrature side before decoding this signal. Since the reset signal is generated independently for each automatic equalizing circuit, there is an effect that the automatic equalizing circuit can be appropriately reset.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a block diagram of an error pulse generator 6 used in the automatic equalizer of the present embodiment.

FIG. 3 is a diagram illustrating the operation of an error pulse generator 6.
(A) is an eye pattern of the in-phase baseband signal _S2P ,
(B) is a signal waveform of the full-wave rectified signal S61 when no noise is added, and (c) is a signal waveform of the full-wave rectified signal S61 when noise is added.

FIG. 4 is a block diagram of an identification circuit 7 used in the automatic equalizer of the present embodiment.

FIG. 5 is a block diagram of a transmission device and a reception device applied to the coded modulation scheme.

[Explanation of symbols]

 Reference Signs List 1 demodulation circuit 101 input terminal 102 distribution circuit (H) 103, 104 multiplication circuit 105 voltage controlled oscillation circuit 106 π / 2 phase shift circuit 107, 108 low-pass filter 2 automatic equalization circuit 21, 22 transversal equalization circuit Reference Signs List 201 tap control circuit 202, 203 delay line with tap 204 adder 205 determination circuit 23 phase control signal generation circuit 3 reception code processing circuit 4, 5 analog / digital conversion circuit (A / D) 6, 7 error pulse generator (EPG ) 61 Full-wave rectifier circuit 62 Flip-flop (F / F) 63 AND circuit 8,9 Identification circuit 81,82 Counter 83 RS flip-flop

Claims (3)

(57) [Claims] A demodulation circuit for synchronously detecting a digital multilevel modulation signal to generate an in-phase baseband signal and a quadrature baseband signal orthogonal to the in-phase baseband signal; and a demodulation circuit for converting the in-phase baseband signal into a first digital signal. A first digital-to-analog converter circuit, a second analog-to-digital converter circuit for converting the quadrature baseband signal into a second digital signal, the first digital signal and the second digital signal Receiving means for generating an in-phase data signal and a quadrature data signal, each of which compensates for intersymbol interference between the first digital signal and the second digital signal, respectively, and a first reset signal and a second reset signal. Reset means respectively responding to the signal and resetting the automatic equalizing means corresponding to the reset signal , Receiving an in-phase baseband signal and converting a first error pulse corresponding to waveform deterioration of the in-phase baseband signal into a clock signal.
A first error pulse generator that is generated synchronously, and a first identification circuit that generates the first reset signal when the number of the first error pulses exceeds a predetermined first threshold value within a predetermined period. Receiving the orthogonal baseband signal and generating a second error pulse corresponding to the waveform deterioration of the orthogonal baseband signal in synchronization with the clock signal .
Error pulse generator, and the second
And a second identification circuit that generates the second reset signal when the number of error pulses exceeds a predetermined second threshold value. 2. Each of the first and second error pulse generators respectively generates the error pulse corresponding to the convergence point spread of a signal obtained by full-wave rectifying the baseband signal. The reset method of the automatic equalizer according to claim 1, wherein: 3. Each of the first and second error pulse generators has a full-wave rectifier circuit for full-wave rectifying the baseband signal, and a level of the full-wave rectified baseband signal is predetermined. 3. The automatic equalizer reset method according to claim 2, further comprising: a flip-flop circuit that outputs a predetermined logical value each time the threshold value is exceeded.