JP3068440B2 - Automatic adaptive equalizer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic adaptive equalizer used for multilevel digital / microwave radio communication, and more particularly to a control signal for generating a control signal for a distortion equalizer circuit provided in the equalizer. The present invention relates to an automatic adaptive equalizer with an improved generation circuit.

[0002]

2. Description of the Related Art In digital / microwave wireless communication technology, line deterioration and instantaneous interruption occur due to waveform distortion caused by multipath fading occurring in a transmission path. Therefore, conventionally, a compensation technique using an automatic adaptive equalizer has been used to compensate for the waveform distortion in the transmission path.

FIG. 4 is a block diagram showing an example of the configuration of a digital demodulator using a conventional automatic adaptive equalizer. The automatic adaptive equalizer 70 equalizes the waveform distortion generated on the transmission line in the distortion equalization circuit 71 and outputs the digital modulation wave signal input from the input terminal 30. The modulated wave whose waveform has been equalized is demodulated by the demodulator 20.

The demodulator 20 performs quadrature synchronous detection on the input digital modulation signal using a carrier synchronized with a carrier modulated on the transmission side. Then, the data signals of the P and Q channels sent from the transmitting side are discriminated and reproduced by an analog-to-digital converter (not shown), and are used as output signals of the demodulator 20. The MSB (Most Significant Bib) of each of the data signals of the P and Q channels
t) is output as quadrant determination signals Dp and Dq, and the next bit (for example, the fourth bit in the case of 64QAM) of the data signal is output as error signals Ep and Eq. The signal is input to the generation circuit 72.

The control signal generating circuit 72 includes a control signal generator 73, an averaging circuit 74, and a fluctuation detecting circuit 75. The control signal generator 73 outputs an interference control signal 101 for equalizing waveform distortion by calculating a correlation between the quadrant determination signal and the error signal.

The averaging circuit 74 averages the interference control signal 101 based on the set time constant and outputs an equalization circuit control signal 102. The averaging circuit 74 can change the set value of the time constant by the time constant control signal 103 input from the outside.

The fluctuation detecting circuit 75 includes the averaging circuit 74.
And outputs a time constant control signal 103 for controlling the time constant of the averaging circuit 74. FIG. 5 shows an example of the configuration of the fluctuation detection circuit 75. The illustrated fluctuation detection circuit 75A includes a rectification circuit 81 that rectifies the equalization circuit control signal 102 output from the averaging circuit 74, and a differentiation circuit 82 that differentiates the output of the rectification circuit 81.

According to the automatic adaptive equalizer 70 having this configuration, the control signal generator 73 outputs the input quadrant determination signal D
An interference control signal 101 for waveform-equalizing multipath fading generated in a transmission path is generated in accordance with p and Dq and error signals Ep and Eq, and is output to an averaging circuit 74. The averaging circuit 74 generates an equalization circuit control signal 102 based on the input interference control signal 101 and sends it to the distortion equalization circuit 11 to execute the distortion equalization. At this time, the equalization circuit control signal 102 which is the output waveform of the averaging circuit 74
Changes according to the interference control signal 101 in response to fading in the transmission path. Then, the averaging circuit 74 determines the averaging time, that is, the ability to follow the fading in accordance with the time constant, and increases the time constant when the variation of the distortion amount is small. Reduces the time constant.

However, when the time constant is small, the control signal fluctuates to degrade the error rate characteristic. When the time constant is large, the fluctuation is eliminated and the error rate characteristic is improved. Therefore, when the distortion amount fluctuation is small, a sufficiently large time constant is set so that the error rate characteristic is more important than the characteristic that follows the fading is increased. When the distortion amount fluctuates with time, the time constant is reduced within a range in which the deterioration of the error rate characteristic can be tolerated so that the characteristic following the fluctuation of the fading becomes higher. As a result, a distortion equalizing circuit 71 having excellent tracking characteristics with respect to a change in distortion amount can be realized.

Next, with reference to FIG. 6, the operation principle of the control of the time constant by the averaging circuit 74 in the fluctuation detecting circuit 75A will be described. FIG. 6 shows the output waveforms of the averaging circuit 74 and the differentiating circuit 82 of the fluctuation detecting circuit 75A in comparison. The equalization circuit control signal 102 changes in response to fading on the transmission path. In the figure, the waveform on the time axis is (a) when there is no fading.
(B) shows a fading variation, (c) shows a regular fading with respect to the elapse of time, (d) shows the fading in (a), and shows the inverse characteristic fading.

In the case of (a) at the time of no fading, the equalization circuit control signal 102 becomes constant. At this time, the rectifier circuit 8
Even if the equalization circuit control signal 102 is rectified by 1, it becomes constant even if it is rectified. Therefore, the fluctuation amount is 0, that is, the differentiating circuit 82 keeps outputting a constant value time constant control signal which is an initial value. In addition, when there is no fading (a), it is not necessary to always keep the following ability high, so that a sufficiently large time constant is set so as to emphasize the error rate characteristics.

In the case of the fading fluctuation shown in FIG. 2B, a gradient is generated in the equalization circuit control signal 102, and the gradient is changed by the rectifier circuit 8.
The variance is obtained by rectification at 1, and the differentiator 82 outputs the rate of change over a certain period of time. At this time, since the ability to follow fading must be high, the differentiation circuit 82
, The time constant of the averaging circuit 74 is reduced.

In the case of constant fading in (c),
The equalization circuit control signal 102 is constant as in the case of (a) without fading. Therefore, the differentiating circuit 82 continues to output the constant value time constant control signal 103 which is the initial value. Further, since it is not necessary to keep the ability to follow fading always high, a sufficiently large time constant is set so as to emphasize the error rate characteristics.

In the case of (d) reverse polarity fading,
The slope of the sign opposite to that in the case of the fading change (a) occurs. However, the slope is rectified by the rectifier circuit 81 and the difference, that is, the absolute value is obtained, so that the differentiating circuit 82 outputs the change rate of the same sign. Therefore, similarly, since the ability to follow fading must be high, the time constant of the averaging circuit 74 is reduced by the time constant control signal 103 from the differentiating circuit 82.

FIG. 7 shows an example of the configuration when the fluctuation detecting circuit 75 is a digital circuit. FIG. 8 is a timing chart of each unit in this case. Illustrated fluctuation detection circuit 7
5B is a flip-flop (F / F) circuit 91, a missing clock generation circuit 92, a delay circuit 93 for delaying an output signal 302 of the F / F circuit 91, and a delay with the output signal 302 of the F / F circuit 91. It comprises a subtractor 94 for calculating the difference between the output signals 303 of the circuit 93.

In this case, in order to control the interference control signal 101 fluctuating for each clock with a sufficient integration time constant, for example, if the integration time is 50 msec and the clock frequency is 25 MHz, the number of data to be integrated is 125 Since the number is 10,000, the equalization circuit control signal 102 is 21
Requires more digits than bits. Therefore, each block in the fluctuation detection circuit 75B requires a circuit of 21 bits or more. The operation principle is that the difference between the equalization circuit control signal 102 and the output signal 303 of the delay circuit 93 is calculated by the subtractor 94, and the calculation result is used as the time constant control signal 103. The time constant control algorithm is the same as that of the case where the analog circuit is used.
When the difference between the three output signals is large, the time constant is controlled to be small, and when the difference is small, the time constant is controlled to be large.

Conventionally, as a technique for guaranteeing waveform distortion in a transmission line by using this kind of automatic adaptive equalizer, for example, JP-A-59-194540, or JP-A-3-2540.
There is a technique disclosed in 84025.

[0018]

As described above, the conventional automatic adaptive equalizer detects a waveform change from an equalizer control signal which is a continuous change amount. for that reason,
When the fluctuation detecting means in the automatic adaptive equalizer is configured by an analog circuit, a differentiating / rectifying circuit of the analog signal must be configured, which requires adjustment work and is inferior in stability.
There is a disadvantage that the circuit cannot be reduced in size and power consumption cannot be reduced.

In the case where the fluctuation detecting means is constituted by a digital circuit and the equalization circuit control signal is a digital signal having a discontinuous change amount, the equalization circuit control signal is given a sufficient time constant and the fluctuation of the signal is obtained. In order to reduce the error rate and improve the error rate characteristics, the equalization circuit control signal needs to be multi-bit.Therefore, an averaging circuit, a delay circuit, and a subtractor having a large number of digits must be prepared. However, there is a drawback that a large-scale circuit configuration is required, and the circuit cannot be reduced in size and consumes low power.

An object of the present invention is to eliminate the above-mentioned disadvantages of the prior art, and to sufficiently reduce the error rate characteristics when the distortion of the transmission line is constant, and to provide a sufficient waveform and the like for the transmission line distortion that fluctuates with time. It is an object of the present invention to provide an automatic adaptive equalizer that can be implemented with good stability, has a small circuit size, and easily consumes low power.

[0021]

To achieve the above object, according to an aspect of an automatic adaptive equalizer of the present invention, a distortion equalization circuit for equalizing waveform distortion of the input modulated wave, the distortion equalization circuit A control signal generation circuit for generating a control signal for controlling the output of the control signal generation circuit, wherein the control signal generation circuit generates a control signal from a baseband signal obtained by demodulating a modulation wave output from the distortion equalization circuit. An interference control signal generating means for outputting an interference control signal based on the error signal and the quadrant determination signal, and an averaging means for averaging the interference control signal output by the interference control generating means; Each timing of the interference control signal of the multi-bit digital signal from the interference control generating means and a signal obtained by delaying the interference control signal
And a variation detecting means for monitoring a difference between each of them, detecting a temporal variation rate according to the difference, and controlling a time constant used for the averaging operation in the averaging means.

In another aspect, the fluctuation detecting means includes: a counting circuit for counting an output signal of the interference control generating means per unit time; and a time constant of the averaging means by calculating a difference between outputs of the counting circuit. And a difference detection circuit for controlling

In another preferred embodiment, the counting circuit receives the interference control signal output from the interference control signal generating means and a clock signal, and performs a count control, and receives the clock signal as an input. A clock generation circuit that outputs a divided clock signal, a first delay circuit that receives the clock signal divided in the previous period and outputs a reset signal of the reversible counter, and an output signal of the reversible counter. And a flip-flop circuit for receiving the divided clock signal, outputting a count result per unit time, and sending the result to the difference detection circuit.

Further, in another preferred aspect, the difference detection circuit receives the count result of the counting circuit, delays the timing by one pulse, and outputs the delayed result. And a subtractor that receives the output signal of the second delay circuit, calculates the difference between the two signals, and outputs the difference as a time constant control signal.

In another preferred embodiment, the fluctuation detecting means detects a temporal fluctuation of the output signal of the interference control generating means, and increases the time constant when the fluctuation is small, and increases the time constant when the fluctuation is large. Control to reduce the time constant is performed.

[0026]

According to the present invention, the fluctuation detecting means detects the temporal fluctuation rate of the interference control signal and controls the time constant of the averaging processing of the interference control signal by the averaging means. The distortion equalization circuit can be controlled so that appropriate distortion equalization can be performed in accordance with the variation of.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of an automatic adaptive equalizer according to one embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of the fluctuation detection circuit 15 constituting the automatic adaptive equalizer 10 of FIG.

In FIG. 1, when a digitally modulated wave is input from an input terminal 30, an automatic adaptive equalizer 10 equalizes waveform distortion generated in a transmission line and outputs the equalized waveform. The modulated wave whose waveform has been equalized is demodulated by the demodulator 20. Among the baseband signals reproduced by the demodulator 20, the representation determination signal D
p, Dq and error signals Ep, Eq are automatically adaptive equalizers 1
It is fed back to 0.

As shown in the figure, the automatic adaptive equalizer 10 of the present embodiment generates a distortion equalizer 11 for equalizing waveform distortion in a transmission path and a control signal for controlling the distortion equalizer 11. And a control signal generation circuit 12.

The control signal generation circuit 12 includes a control signal generator 13, an averaging circuit 14, and a fluctuation detection circuit 15. The control signal generator 13 outputs the quadrant determination signals Dp, D
By calculating the correlation between q and the error signals Ep and Eq, an interference control signal 101 for equalizing waveform distortion is output.

The averaging circuit 14 averages the interference control signal 101 based on the set time constant and outputs an equalization circuit control signal 102. The averaging circuit 14 can change the set value of the time constant by the time constant control signal 103 input from the outside.

As shown in FIG. 2, the fluctuation detecting circuit 15
It comprises a counting circuit 50 and a difference detection circuit 60. Then, the interference control signal 101 output from the control signal generator 13 is counted by the counting circuit 50, and the difference detection circuit 6
At 0, the fluctuation per unit time is detected. The detection result is used as a time constant control signal 103 to control the time constant of the averaging circuit 14.

The counting circuit 50 includes a reversible counter 51, a missing clock generation circuit 52, a delay circuit 53, and a flip-flop (F / F) circuit 54. The difference detection circuit 60 includes a subtracter 61 and a delay circuit 62.

FIG. 3 shows an interference control signal 101, a count timing clock 201, and a reset signal 203, which are input signals of a reversible counting circuit 51 in the counting circuit 50 shown in FIG.
When the output signal ^{(2 3,} 2 ^{2, 2} 1, 2 0) 213,21
2, 211 and 210, a pulse signal 202 which is a clock signal for the F / F circuit 54, and a counting result 2 of the counting circuit 50
21 is a timing chart of each unit showing the respective timings of FIG. FIG. 3 shows a case where the interference control signals 101 are all “1”.

Next, the operation of this embodiment will be described with reference to FIGS. When a digital modulation wave is input from the input terminal 30, the automatic adaptive equalizer 10
Waveform distortion generated in the transmission path is equalized and output. The modulated wave whose waveform has been equalized is demodulated by the demodulator 20.

The demodulator 20 performs quadrature synchronous detection on the input digital modulation signal using a carrier synchronized with the carrier modulated on the transmission side, and discriminates and reproduces the P and Q channel data signals sent from the transmission side (not shown). Then, the output signal of the demodulator 20 is used. The MSB (Most Signfifi) of each of the P and Q channel data signals
cant Bit) are the quadrant determination signals Dp and Dq,
Also, the next bit of the least significant bit of the data signal (for example,
The fourth bit in the case of 64QAM) is the error signal Ep, Eq
And output to the control signal generation circuit 12.

In the control signal generation circuit 12, the control signal generator 13 outputs the input quadrant determination signals Dp and Dq,
By calculating the correlation between the error signals Ep and Eq, an interference control signal 101 for waveform equalizing multipath fading generated in the transmission path is generated and sent to the averaging circuit 14.

The averaging circuit 14 generates an equalization circuit control signal 102 by averaging the input interference control signal 101 and sends it to the distortion equalization circuit 11 to execute distortion equalization. . At this time, the equalization circuit control signal 102 which is the output waveform of the averaging circuit 14 is the interference control signal 101
And changes in response to fading in the transmission path. Also, the averaging circuit 14 changes the time constant by setting the time constant control signal 103 input from the fluctuation detecting circuit 15, so that the averaging circuit 14 exhibits a sufficient ability to follow the multipath fading fluctuation occurring in the transmission path. And the error rate characteristic can be maintained in an optimum state.

The interference control signal 101 input to the fluctuation detecting circuit 15 is a count signal of the reversible counting circuit 51. When the interference control signal 101 is "1", +1 is counted and "0".
In the case of -1, -1 is counted. Further, a clock 201 for counting timing is input to the reversible counting circuit 51, and counting timing control is performed. In FIG. 2, a four-stage counter is shown as an example, but the number of stages is actually determined by the averaging time, and only the upper few bits may be output during the counting.

The clock 201 for counting timing, which is input simultaneously with the interference control signal 101, is also input to the missing clock generation circuit 52, and after the clock frequency division is performed,
A pulse signal 202 having a pulse signal for one clock is output during a prescribed number of clocks 201 for counting timing. As the degree of frequency division, a degree that does not cause overflow even when the inputs to the reversible counter 51 are all “1” or “0” is selected.

One of the frequency-divided pulse signals 202 is output to the delay circuit 53 and the other is output to the F / F circuit 54. The delay circuit 58 is １ ／ of the count timing clock.
A reset signal 203 delayed by a period is output. The reversible counting circuit 51 resets the count of the reversible counting circuit 51 by the reset signal 203, whereby the reversible counting circuit 51 starts counting again. The output of the reversible counting circuit 51 is
The signal is input to the F / F circuit 54.

The F / F circuit 54 outputs a count result per unit time at the timing of the divided pulse signal 202. For example, the integration time in the averaging circuit is set to 50 ms.
c, when the clock frequency is 25 MHz, the number of data to be integrated is 1.25 million, and the reversible counter 51 is 21
Although the number of digits of bits or more is necessary, since only a rough difference at each timing needs to be known, only the upper few bits of the counted data may be output. Therefore, in this case, each block in the fluctuation detection circuit 15 is
For 1, a circuit of 21 bits or more is required,
Other F / F circuit 54, subtractor 61, delay circuit 62
Can be configured with a circuit having a smaller number of bits.

The difference detection circuit 60 branches the signal output from the counting circuit 50 into two, one of which is directly input to a subtracter 61 and the other of which is input to a delay circuit 62. The delay circuit 62 delays the count result 221 by one pulse signal and outputs the result. The two signals having different timings by one pulse signal are input to a subtractor 61, and then the difference between the two signals is calculated.
Output to the time constant circuit.

Here, when there is no fading or when the fading is constant, no difference appears for each time slot, so that the time constant control signal 108 is output as 0. At this time, since it is not necessary to keep the tracking characteristic high at all times, a sufficiently large time constant is set so as to emphasize the error rate characteristic. In addition, when the fading amount changes with time, a difference appears at each timing. Therefore, the time constant is reduced so that the following characteristic with respect to the fading becomes high.

In the averaging circuit 14, the ability to follow the fading is determined according to the averaging time, that is, the time constant. Control is performed so that the equalization circuit control signal 102 has no fluctuation by giving priority to the error rate characteristic. When the amount of distortion varies with time, control is performed so that the time constant is reduced and the ability to follow fading is increased.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not necessarily limited to the above embodiments.

[0047]

As described above, according to the present invention,
If the amount of waveform distortion of the modulated wave is constant, a large time constant is output and an equalizing circuit control signal with small fluctuation is output.If the amount of distortion changes, the time constant is adjusted according to the amount of change. And output the equalization circuit control signal, so that it is possible to sufficiently perform waveform equalization even for transmission line distortion that fluctuates with time without deteriorating the error rate characteristics when the transmission line distortion is constant. it can.

Further, since the time constant of the averaging circuit is controlled by detecting a temporal variation of the interference control signal which is a digital signal, the variation detecting circuit can be easily constituted by a digital circuit. That is, as compared with the case where the fluctuation detection circuit is configured by an analog circuit, it is possible to obtain a stable control signal that does not require an adjustment operation.

Further, if the circuit is incorporated in the LSI, the circuit can be reduced in size and power consumption can be reduced, so that the circuit can be realized at low cost and easily.

Further, even when the fluctuation detecting circuit is constituted by a digital circuit, the circuit scale in the fluctuation detecting circuit is smaller than in the conventional case, so that the circuit can be easily reduced in size and power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an automatic adaptive equalizer according to one embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a fluctuation detection circuit according to the embodiment.

FIG. 3 is a chart showing input / output waveforms of various parts of the counting circuit according to the embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional automatic adaptive equalizer.

FIG. 5 is a block diagram showing a configuration example of an analog circuit of the fluctuation detection circuit of FIG. 4;

FIG. 6 is a chart showing a control state of a time constant of an averaging circuit by the fluctuation detection circuit of FIG. 4;

FIG. 7 is a block diagram showing an example of a configuration of a fluctuation detection circuit of FIG. 4 using a digital circuit;

8 is a chart showing input / output waveforms of various parts of the fluctuation detection circuit of FIG. 7;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Automatic adaptive equalizer 11 Distortion equalization circuit 12 Control signal generation circuit 13 Control signal generator 14 Averaging circuit 15 Fluctuation detection circuit 20 Demodulator 50 Counting circuit 51 Reversible counter 52 Toothless clock generation circuit 53, 62 Delay Circuit 54 Flip-flop circuit 60 Difference detection circuit 61 Subtractor

Claims (7)

(57) [Claims] With a 1. A distortion equalization circuit for equalizing waveform distortion of the input modulated wave, and a control signal generating circuit for generating a control signal for controlling the output of the strain equalization circuit, the control A signal generation circuit configured to output an interference control signal based on an error signal and a quadrant determination signal generated from a baseband signal obtained by demodulating the modulated wave output from the distortion equalization circuit; When the averaging means for operating averaged over outputted the interference control signal by the interference control generating means, before <br/> Symbol interference control signal multi-bit digital signal from the interference control generating means and the Interference control signal with delayed signal
Monitoring the difference at each timing , detecting a temporal variation rate according to the difference, and controlling a time constant used for an averaging operation in the averaging means. Type equalizer. 2. The automatic adaptive equalizer according to claim 1, wherein said fluctuation detecting means is a digital circuit. 3. The fluctuation detecting means includes: a counting circuit that counts the interference control signal output from the interference control generating means for each unit time; and a difference between outputs of the counting circuit. The automatic adaptive equalizer according to claim 2, further comprising a difference detection circuit that controls a time constant. 4. A reversible counting circuit for inputting the interference control signal and a clock signal output from the interference control signal generating means and performing count control, and for inputting and dividing the clock signal. A missing clock generating circuit for outputting, a first delay circuit for inputting the frequency-divided clock signal and outputting a reset signal of the reversible counter, and an output signal of the reversible counter and the divided signal 4. The automatic adaptive equalizer according to claim 3, further comprising: a flip-flop circuit that inputs a clock signal, outputs a count result per unit time, and sends the result to the difference detection circuit. 5. The differential detection circuit, comprising: a second delay circuit that receives a count result of the count circuit and outputs the delayed one-pulse timing; and a count result of the count circuit and the second delay circuit. 4. The automatic adaptive equalizer according to claim 3, further comprising: a subtractor that inputs the output signal of the first and second signals and calculates a difference between the two signals and outputs the difference as a time constant control signal. 6. The differential detection circuit, comprising: a second delay circuit that receives an output signal of the flip-flop circuit and outputs the delayed signal by one pulse, and an output signal of the flip-flop circuit and the second signal. 5. The automatic adaptive equalizer according to claim 4, further comprising: a subtractor that receives an output signal of the delay circuit, calculates a difference between the two signals, and outputs the difference as a time constant control signal. 7. The fluctuation detecting means detects a temporal fluctuation of the interference control signal output from the interference control generating means, and increases the time constant when the fluctuation is small, and increases the time constant when the fluctuation is large. 6. The automatic adaptive equalizer according to claim 1, wherein control is performed to reduce a time constant.