JP3029283B2 - Frame synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a digital microwave radio communication system employing a multi-level quadrature amplitude modulation system, such as a terrestrial microwave radio communication system. In particular, the present invention relates to a frame synchronization method used when performing error correction processing in a state where differential conversion processing is performed on a transmission signal.

(Prior Art) In recent years, as one of transmission systems of digital microwave communication, a 22- ^m value (m = 1, 2, 3,...) Quadrature amplitude modulation (QAM: Quadr
ature Ampletude Modulation).
This QAM system transmits digital data by changing both the amplitude and the phase of a carrier wave, and can realize more efficient transmission.

By the way, in systems using this type of system recently, multi-leveling has been advanced from 16QAM modulation system to 64QAM modulation system and 256QAM modulation system.Accordingly, the amplitude characteristics, delay characteristics, linearity, etc. There is a demand for higher precision. However, there is a certain limit to improving the accuracy of hardware, and the BER for C / N that indicates the performance of communication equipment
The characteristic is that the BER does not decrease below a certain value, and the residual BER occurs.

Therefore, as an effective means for reducing the residual BER, an error correction circuit has been conventionally used. As the error correction code, a block code represented by, for example, a BCH code or a Reed-Solomon code is generally used. When performing an error correction process using this block code,
Since it is necessary to know the delimiter of each block, the communication device on the receiving side needs to establish frame synchronization with the received signal.

On the other hand, in a digital microwave radio communication system,
A differential conversion process is performed to remove the position uncertainty of the reproduced carrier wave generated in the communication device on the receiving side. The differential conversion process is a process in which a transmission-side communication device performs a summation operation on a transmission code and transmits the transmission code, and a reception-side communication device performs a difference operation on the received code. However, if this differential conversion process is used, the error that occurs in the transmission code on the transmission path is doubled when the difference is calculated by the receiving-side communication device. This leads to a decrease in correction ability. For this reason, the error correction processing is generally performed between the sum operation and the difference operation, that is, inside the differential logic.

(Problems to be Solved by the Invention) However, when the error correction processing is performed inside the differential logic as described above, the following problem occurs. That is, when a block code is used as an error correction code as described above, it is necessary to establish frame synchronization in a communication device on the receiving side in order to know the delimitation of the block. However, when frame synchronization is attempted before the difference calculation, the phase of the frame synchronization signal takes four patterns depending on whether the phase of the reproduced carrier wave is 0 °, 90 °, 180 °, or 270 °. obtain. Therefore, when a correct pattern cannot be detected, frame synchronization cannot be established, which causes a problem that accurate error correction cannot be performed.

Therefore, the present invention focuses on the above circumstances, so that even if there are a plurality of signal patterns of the received frame synchronization signal due to the phase uncertainty of the reproduced carrier, the frame synchronization can always be accurately performed, thereby achieving accurate error correction. It is an object of the present invention to provide a frame synchronization method capable of performing the following.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a transmitting device,
The binary digital signal is subjected to a summation operation in accordance with a differential conversion method based on a predetermined signal point arrangement, and then subjected to error correction coding, and then to multi-level quadrature amplitude modulation and transmitted. The apparatus performs multi-level quadrature amplitude demodulation on the received signal, and then performs error correction decoding, and then performs a difference operation process in accordance with the differential conversion scheme to reproduce binary digital data. In a communication system, a transmitting apparatus adds a frame synchronization signal having a signal pattern set in advance according to a signal point arrangement of a differential conversion method to a transmission signal and transmits the transmission signal. A signal pattern in which the frame synchronization signal sent from the receiver changes due to the phase rotation of the reproduced carrier is stored in advance as a comparison pattern and demodulated. The signal pattern of the frame synchronization signal is compared with the comparison pattern, and frame synchronization is established based on the comparison result.

(Operation) As a result, according to the present invention, from the transmitting side apparatus, for each signal point arrangement of the differential conversion method, that is, for each of the signal point arrangements such as the rotational symmetry arrangement, the gray arrangement and the natural binary arrangement, A frame synchronization signal having a set signal pattern is transmitted, and the receiving apparatus prepares in advance a change pattern of the transmission frame synchronization signal caused by the phase rotation of the reproduced carrier, and the signal pattern of the demodulated frame synchronization signal is provided. Frame synchronization is established based on the result of comparison between the frame pattern and the change pattern. For this reason, even if there are a plurality of signal patterns of the received frame synchronization signal due to the phase uncertainty of the reproduced carrier, it is possible to always accurately establish the frame synchronization. Therefore, even if a block code is used as the error correction code, the delimiter of each block can be accurately determined, and thereby accurate error correction processing can be performed.

Embodiment 1 First Embodiment This embodiment shows a case where a rotationally symmetric arrangement type differential conversion system is used as the differential conversion system.

FIG. 1 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which a frame synchronization system according to a first embodiment is applied.
B indicates a wireless device on the receiving side.

The transmitting-side radio device A includes a transmission digital signal processing unit (T-DPU) 10 for performing predetermined signal processing on a transmission digital signal output from a terminal device (not shown), a modulation unit 20, and a modulation unit 20. The output transmission digital signal is converted to microwave and transmitted
And a transmission unit (TX) 30 for wireless transmission from the transmission unit 31.

The modulation unit 20 includes a rotationally symmetric arrangement type sum calculation circuit (SUMLOG) 21, a speed conversion circuit (SPDCONV) 22,
Frame insertion circuit (FRMINS) 23, error correction circuit encoder (FECENC) 24, 64-ary quadrature amplitude modulation circuit (64QAMMOD) 25
It is composed of The frame insertion circuit 23 generates a frame synchronization signal having a predetermined signal pattern set in advance according to the rotationally symmetric arrangement type differential conversion system. To be added.

On the other hand, the wireless device B on the receiving side is the wireless device A on the transmitting side.
Receiving unit (RX) 40 that receives a microwave signal transmitted from a wireless line via receiving antennas 41 and 42
And Space Diversity Synthesis Unit (SDCOMB) 50
, A fading automatic equalization unit (EQL) 60, a demodulation unit 70, and a reception digital signal processing unit (R =
DPU) 80.

The demodulation unit 70 includes a 64-ary quadrature amplitude demodulation circuit (64QAMDEM) 71, a frame synchronization circuit (FRMREC) 72,
Error correction circuit decoder (FECDEC) 73 and speed conversion circuit (SP
DCONV) 74 and rotationally symmetric arrangement type difference calculation circuit (DIFLOG) 7
It consists of five. The frame synchronization circuit 72 stores and holds a comparison signal pattern preset according to the rotationally symmetric arrangement type differential conversion method, and compares the signal pattern of the demodulated frame synchronization signal with the comparison signal pattern. Is used to establish frame synchronization.

By the way, the frame insertion circuit 23 of the wireless device A on the transmission side.
In the above, the signal pattern of the frame synchronization signal added to the transmission digital signal and the comparison signal pattern stored and held in the frame synchronization circuit 72 of the wireless device B on the receiving side are:
Each is set as follows.

That is, generally, in 64QAM, as shown in FIG.
Of the binary pulses in the sequence, the highest two sequences (a ₁ , a ₂ ) are in the first pass, the lower two sequences (a ₃ , a ₄ ) are in the second pass, and the lowest two sequences (a ₅₎ , a ₆ ) is called the third pass. As one method for improving the bit error rate characteristics, a rotationally symmetric arrangement type differential conversion method is employed.

FIG. 2 shows the signal point arrangement of this method.
Indicates a first pass, () indicates a second pass, and no parentheses indicate a third pass. As shown in the figure, in the signal point arrangement of the rotationally symmetric arrangement type, the signal of the first path is made to correspond to the signal representing the quadrant, the sum difference operation is performed, and the signal of the second path and lower is gray-coded. Later, the code of the second pass represented by 2 bits in the first quadrant is rotationally symmetrically assigned to the other quadrants. With such a signal point arrangement,
As can be seen from FIG. 2, the signals of the second path and the third path are the same in each quadrant, and only the first path is different in each quadrant. Therefore, when performing the differential conversion, it is necessary to perform only the first pass, and the second pass and the third pass are performed.
Not required for paths.

Then, in the modulation / demodulation method using the rotationally symmetric arrangement type differential conversion, a change in the signal pattern of the received digital signal due to the influence of the phase uncertainty of the reproduced carrier at the receiving side is as shown in FIG. The signals x ₁ , y ₁ ,
x _2, y ₂ ... ... x _m, subscript numerals 1, 2 y _m, ..., m the first pass, respectively, the second pass, ..., representing the m-th path. As is apparent from FIG. 3, in the rotationally symmetric arrangement, the demodulated digital signal before the difference processing is performed by the receiving-side radio device is such that when the reproduced carrier wave becomes 0 °, 90 °, 180 °, 270 °, The first pass is (x ₁ , y ₁ ), (y ₁ , ▲ ▼), (▲ ▼, ▲
▼), (▲ ▼, x ₁ ), but the signal following the second pass is the same no matter which phase is pulled in.

Of these, the first pass represents all four cases with two bits, so it is not necessary to compare the frame synchronization bits, and it can be seen that only one pattern is sufficient for the second and subsequent passes.

Therefore, in the frame insertion circuit 23 of the wireless device A on the transmitting side, (x ₂ , x ₃ , y ₂ , y ₃ ) is used as the signal pattern of the frame synchronization signal added to the transmission digital signal. On the other hand, in the frame synchronization circuit 72 of the wireless device B on the receiving side, (x ₂ , x ₃ , y ₂ , y ₃ ) is prepared and stored as a comparison signal pattern.

Because of such a configuration, first, the wireless device A on the transmitting side
Then, the following operation is performed. That is, the transmission digital signals a _{1 to} a ₆ output from the transmission digital signal processing unit 10 are first subjected to a sum operation by a rotationally symmetric arrangement type differential conversion system in a sum operation circuit 21, and then to a speed conversion circuit the frame sync signal in frame insertion circuit 23 after the speed conversion is performed in _{22 (x 2, x 3,} y 2, y 3) is added. Then, the transmission digital signal to which the frame synchronization signal is added is subjected to error correction encoding processing using a block code in an error correction circuit encoder 24,
The signal is modulated by the 64-ary quadrature amplitude modulation circuit 25, further frequency-converted into a microwave by the transmission unit 30, and transmitted by radio from the transmission antenna 31.

On the other hand, the following operation is performed in the wireless device B on the receiving side. That is, the microwave signal arriving from the wireless device A on the transmitting side via the wireless line is received by the receiving unit 40 via two receiving antennas 41 and 42 provided for space diversity, and then transmitted to the space unit. The signals are synthesized by the diversity synthesizing unit 50 and further subjected to fading correction by the fading automatic equalizing unit 60, and then input to the demodulation unit 70.

In the demodulation unit 70, first, a 64-ary quadrature amplitude demodulation circuit
At 71, the received digital signal is demodulated and then input to the frame synchronization circuit 72. In this frame synchronization circuit 72, the signal pattern of the demodulated frame synchronization signal is stored in advance as a comparison signal pattern (x ₂ , x ₃ , y ₂ , y ₃ ) suitable for rotationally symmetric arrangement type differential conversion. Is compared to determine whether they match. Then, when it is detected that the signal pattern of the demodulated frame synchronization signal matches the comparison signal pattern (x ₂ , x ₃ , y ₂ , y ₃ ), the phase of the demodulated frame synchronization signal at this time is determined. The reception phase is pulled in, and a frame synchronization signal FRM synchronized with this phase is output. For this reason, the error correction circuit decoder 73 correctly performs error correction decoding processing on the demodulated digital signal in synchronization with the frame synchronization signal FRM. The demodulated digital signal subjected to the error correction decoding is speed-converted by the speed conversion circuit 74, and then subjected to a difference calculation process by the difference calculation circuit 75.

As described above, according to the present embodiment, the signal pattern (x ₂ , x ₃ , y ₂ , y ₃ ) set in advance according to the signal point arrangement of the rotationally symmetric arrangement type differential conversion method is transmitted from the transmission side wireless device A. The transmitted frame synchronizing signal (x ₂ , x ₃ , y ₂ , y ₃₎ due to the phase uncertainty of the reproduced carrier is sent to the frame synchronizing circuit 72 of the wireless device B on the receiving side. ) Is stored in advance as a comparison pattern, and the signal pattern of the demodulated frame synchronization signal is compared with this comparison pattern to establish frame synchronization. Therefore, even if there are a plurality of signal patterns of the received frame synchronization signal due to the phase uncertainty of the reproduced carrier, frame synchronization can always be accurately performed. For this reason, the error correction circuit decoder 73 can perform accurate error correction for the correct frame synchronization.

Second Embodiment This embodiment shows a case where a gray layout type differential conversion system is used as the differential conversion system.

FIG. 4 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which the frame synchronization system according to the second embodiment is applied. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

The frame insertion circuit 231 of the wireless device A on the transmission side generates a frame synchronization signal having a predetermined signal pattern set in advance according to the gray layout type differential conversion method. At the beginning of the frame. FIG. 9 shows a signal point arrangement in the gray arrangement type differential conversion system.

On the other hand, the frame synchronization circuit 721 of the wireless device B on the receiving side
Stores and holds a comparison signal pattern preset according to the gray arrangement type differential conversion method, and establishes frame synchronization by comparing the signal pattern of the demodulated frame synchronization signal with the comparison signal pattern. .

By the way, the transmission pattern and the comparison pattern of the frame synchronization signal are set as follows. That is, the phase of the received signal becomes as shown in FIG. 5 due to the phase uncertainty of the reproduced carrier wave, as in the case of the above-described arrangement of the rotation target. Note that the signals x ₁ , y ₁ , x ₂ , y ₂ …… x _m ,
subscript numerals 1, 2 y _m, ..., m is the first pass, respectively, second paths,
.., The m-th path is the same as in the case of FIG. That is, the phase of the recovered carrier is 0 °, 90 °, 180 °,
At 270 °, the first paths of the received signal are (x ₁ ,
y ₁ ), (y ₁ , ▲ ▼), (▲ ▼, ▲ ▼),
(▲ ▼, x ₁ ), and the signals in the second and subsequent paths are (x ₂ , ..., x _m , y ₂ , ..., y _m ), (y ₂ , ..., y _m , x ₂ , …, X _m ), (x ₂ ,…, x _m , y ₂ ,…, y _m ), (y ₂ ,…, y _m , x ₂ ,…, x _m ) and so on (x ₂ ,… , x _m ) and (y ₂ , ..., y _m ) are interchanged. Therefore, if the values of (x ₂ ,..., X _m ) and (y ₂ ,..., Y _m ) are different, depending on the pull-in phase, the demodulated signal pattern and the comparison pattern will be different patterns. As a result, frame synchronization cannot be achieved.

Therefore, the transmit frame sync _{signal, (x 2, x 3,} y 2, y 3) with and _{(x 2, x 3) =} (y 2, y 3) and comprising a pattern, that is (x _2, x ₃ , x ₂ , x ₃ ). Further, (x ₂ , x ₃ , x ₂ , x ₃ ) is set as the comparison pattern, and this is stored and held in the frame synchronization circuit 721.

Because of such a configuration, first, the wireless device A on the transmitting side
In the transmission digital signal, the sum calculation is performed by the sum calculation circuit 211 by the gray arrangement type differential conversion method, and after the speed conversion, the frame synchronization signal (x ₂ , x ₃ , x ₃ ) ₂ , x ₃ ) is added. Then, after performing error correction coding processing, 64QAM modulation is performed, and a transmission unit 30 is added. Then, after being subjected to error correction coding processing, the signal is subjected to 64QAM modulation, frequency-converted into a microwave by the transmission unit 30, and transmitted by radio.

On the other hand, in the wireless device B on the receiving side, the received digital signal subjected to the fading correction is input to the frame synchronization circuit 721 after being subjected to 64QAM demodulation. And
In the frame synchronizing circuit 721, judges that the demodulated frame sync signal is compared with the comparative pattern described previously _{(x 2, x 3, x} 2, x 3), the correct frame synchronizing signal when both patterns match Then, frame synchronization is established. Then, the error correction circuit decoder 73 performs an error correction decoding process in synchronization with the frame signal FRM output from the frame synchronization circuit 721. Therefore, even if a block code is used as the error correction code, correct error correction is always performed.

Third Embodiment This embodiment shows a case where a natural binary arrangement type differential conversion method is used as the differential conversion method.

FIG. 7 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which the frame synchronization system according to the third embodiment is applied. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description is omitted.

The frame insertion circuit 232 of the wireless device A on the transmission side generates a frame synchronization signal having a predetermined signal pattern set in advance according to the natural binary arrangement type differential conversion method, and transmits the frame synchronization signal. It is added to the head of the digital signal frame. FIG. 10 shows the signal point arrangement in the natural binary arrangement type differential conversion system.

On the other hand, the frame synchronization circuit 722 of the wireless device B on the receiving side
A comparison signal pattern preset according to the natural binary arrangement type differential conversion method is stored and held, and frame synchronization is established by comparing a signal pattern of a demodulated frame synchronization signal with the comparison signal pattern. By the way, the transmission pattern and the comparison pattern of the frame synchronization signal are set as follows. That is, as in the case of the above-mentioned arrangement for rotation, the phase of the received signal becomes as shown in FIG. 6 due to the phase uncertainty of the reproduced carrier. Note that signals x ₁ , y ₁ , x ₂ , y ₂ ,.
... x _m , y _m, the subscripts 1, 2, ..., m are the first pass and the second
The path,..., The m-th path is represented in FIG.
This is the same as in the case of FIG. That is, when the phases of the reproduced carrier are 0 °, 90 °, 180 °, and 270 °, the received signals are (x ₁ … x _m , y ₁ … y _m ), (y ₁ … y _m , ▲ ▼. ▼), (▲ ▼… ▲ ▼, ▲… ▲ ▼), (▲ ▼… ▲ ▼, x ₁ … x _m ). Therefore, for example, when compared with a frame synchronization signal demodulated with only one signal pattern of (x ₁ ... x _m , y ₁ ... y _m ), the signal pattern of the demodulated frame synchronization signal is changed by the phase rotation of the reproduced carrier. In the case where the signal pattern is changed to the three types, the determination of the frame synchronization pattern is erroneous, and as a result, the frame synchronization cannot be correctly established.

Therefore, the transmission-side frame insertion circuit 232 adds (x ₁ , x ₂ , x ₃ , y ₁ , y ₂ , y ₃ ) to the transmission digital signal as a transmission frame synchronization signal, the synchronization circuit 732, as a comparison pattern _{(x 1, x 2, x} 3, y 1, y 2, y 3), (y 1, y 2, y 3, ▲ ▼, ▲ ▼, ▲ ▼), ( ▲ ▼, ▲ ▼, ▲ ▼, ▲ ▼, ▲
▼, ▲ ▼), (▲ ▼, ▲ ▼, ▲ ▼, x 1, x 2, x 3) to set the four patterns of be held.

Because of such a configuration, first, the wireless device A on the transmitting side
Then, the transmission digital signal is naturally added to the sum
A summation operation is performed by the binary arrangement type differential conversion method, and after the speed conversion, the frame synchronization signals (x ₁ , x ₂ , x ₃ , y ₁ , y ₂ , y ₃ ) described above are converted by the frame insertion circuit 232. Will be added. Then, after being subjected to error correction coding processing, the signal is subjected to 64QAM modulation, frequency-converted into a microwave by the transmission unit 30, and transmitted by radio.

On the other hand, in the wireless device B on the receiving side, the received digital signal subjected to the fading correction is input to the frame synchronization circuit 722 after being subjected to 64QAM demodulation. And
In this frame synchronization circuit 722, the demodulated frame synchronization signal is obtained by comparing the comparison patterns (x ₁ , x ₂ , x ₃ , y ₁ , y ₂ , y ₃ ), (y ₁ , y ₂ , y ₃ , ▲ ▼) , ▲ ▼, ▲ ▼), (▲ ▼, ▲ ▼, ▲ ▼, ▲ ▼, ▲
▼, ▲ ▼), (▲ ▼, ▲ ▼, ▲ ▼, x 1, x 2, x 3) and are compared respectively, when the found pattern that matches in these comparative patterns, correct frame synchronization signal And frame synchronization is established. Then, the error correction circuit decoder 73 performs an error correction decoding process in synchronization with the frame signal FRM output from the frame synchronization circuit 722. Therefore, even if a block code is used as the error correction code, correct error correction is always performed.

Fourth Embodiment This embodiment shows another example in which a natural binary arrangement type differential conversion method is used as the differential conversion method.

FIG. 8 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which the frame synchronization system according to the fourth embodiment is applied. In this figure, the same parts as those in FIG. 1 are denoted by the same reference numerals.

As mentioned in the third embodiment, the phase rotation of the recovered carrier, the signal pattern of the demodulated frame sync signal _{(x 1 ... x m, y} 1 ... y m), (y 1 ... y m, ▲ ▼… ▲ ▼), (▲ ▼… ▲ ▼, ▲… ▲ ▼), (▲ ▼… ▲ ▼, x ₁ … x _m ). That is, the change pattern due to the rotation phase of the reproduced carrier of the demodulator a frame synchronization signal, together with Waru replacement mutually and patterns I-axis (x ₁ ... x _m) and Q axis of the pattern (y ₁ ... y _m), the code is It will be inverted.

Focusing on this point, (x ₁ … x _m ) and (y ₁ … y _m ) are the same pattern (x ₁ … x _m )
And Then, the frame synchronization circuit of the receiving side, the I axis (x ₁ ... x _m) and (▲ ▼ ... ▲ ▼), similarly in the Q axis (x ₁ ... x _m) and (▲ ▼ ... ▲ ▼ ) Are stored and retained as comparison patterns.

For example, in the case of 64QAM, the frame insertion circuit 233 on the transmitting side prepares (x ₁ , x ₂ , x ₃ ) on the I axis and the Q axis as shown in FIG. Is added to the transmission digital signal. On the other hand, in the frame synchronization circuit 723 on the receiving side, (x ₁ , x ₂ , x ₃ ) and (▲ ▼, ▲ ▼, ▲ ▼) are used as comparison patterns for the I axis.
, And (x ₁ , x ₂ , x ₃ ) and (▲ ▼, ▲ ▼, ▲ ▼) as comparison patterns for the Q axis.
Are respectively stored.

In this way, the frame synchronization circuit 723 on the receiving side converts the signal pattern of the demodulated frame synchronization signal into the comparison patterns (x ₁ , x ₂ , x ₃ ) and (▲ ▼, ▲) for each of the I axis and the Q axis. ▼ 、 ▲ ▼)
By comparing with, the frame synchronization pattern can be correctly detected, and thereby the frame synchronization can be correctly performed. Therefore, even when a block code is used as the error correction code, the delimiter of the block code can be accurately detected, and thereby the error correction decoding process can be performed accurately.

It should be noted that the present invention is not limited to the above embodiments, the configuration of the transmitting-side wireless device and the receiving-side wireless device,
The type of the differential conversion method can be variously modified without departing from the gist of the present invention.

[Effects of the Invention] As described above in detail, the present invention provides a
A frame synchronization signal having a signal pattern set in advance according to the signal point arrangement of the differential conversion method is added to the transmission signal and transmitted. At the receiving device, the frame synchronization signal sent from the transmitting device is a reproduced carrier wave. Is stored in advance as a comparison pattern, the signal pattern of the demodulated frame synchronization signal is compared with the comparison pattern, and frame synchronization is established based on the comparison result. Things.

Therefore, according to the present invention, even if the signal pattern of the received frame synchronization signal has a plurality of patterns due to the phase uncertainty of the reproduced carrier, it is possible to always accurately perform frame synchronization, thereby performing accurate error correction. And a frame synchronization method capable of performing such operations.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which a frame synchronization system according to a first embodiment of the present invention is applied, and FIG. 2 is a signal point in the case of a rotationally symmetric arrangement type differential conversion system. FIG. 3 is a diagram showing an arrangement, FIG. 3 is a diagram showing a change in a reception pattern due to phase uncertainty of a reproduced carrier in the case of a rotationally symmetric arrangement type differential conversion system, and FIG. 4 is a frame in a second embodiment of the present invention. FIG. 5 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which a synchronization system is applied. FIG. 5 is a diagram showing a change in a reception pattern due to phase uncertainty of a reproduced carrier in the case of a gray arrangement type differential conversion system. FIG. 6 is a diagram showing a change in the reception pattern due to the phase uncertainty of the reproduced carrier in the case of the natural binary arrangement type differential conversion system. FIG. 7 is a diagram showing the frame synchronization system in the third embodiment of the present invention. FIG. 8 is a circuit block diagram showing a configuration of a digital microwave radio communication system using the same. FIG. 8 is a circuit block diagram showing a configuration of a digital microwave radio communication system to which a frame synchronization method is applied in a fourth embodiment of the present invention. 9 and 10 are diagrams showing signal point arrangements in the case of the gray arrangement type differential conversion system and the natural binary arrangement type differential conversion system, respectively. A: wireless device on the transmitting side, B: wireless device on the receiving side, 10
…… Transmission digital signal processing unit (T-DPU), 20,
201,202,203 ... Modulation unit, 21,211,212,213 ... Sum calculation circuit (SUMLOG), 22 ... Speed conversion circuit (SPDCON
V), 23,231,232,233 …… Frame insertion circuit (FRMIN
S), 24: Error correction circuit encoder (FECENC), 25: 64
Value quadrature amplitude modulation circuit (64QAMMOD), 30: transmission unit (TX), 31: transmission antenna, 40: reception unit (R
X), 41, 42 ... receiving antenna, 50 ... space diversity combining unit (SDCOMB), 60 ... automatic fading equalization unit (EQL), 70, 701, 702, 703 ... demodulation unit, 71 ... 64 value quadrature amplitude demodulation circuit ( 64QAMDEM), 72,7
21,722,723: Frame synchronization circuit (FRMREC) 73: Error correction decoder (FECDEC) 74: Speed conversion circuit (SPDCON)
V), 75, 751, 752, 753 ... Difference calculation circuit (DIFLOG), 80
...... Reception digital signal processing unit (R-DPU).

Continuation of the front page (56) References JP-A-4-129448 (JP, A) JP-A-62-247655 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04L 27 / 34 H04J 3/06 H04L 7/08

Claims (5)

(57) [Claims] 1. A transmitter device performs a summation operation on a binary digital signal in accordance with a differential conversion method based on a predetermined signal point arrangement, and then performs error correction encoding, and then performs multilevel quadrature amplitude. The receiving side device performs multi-level quadrature amplitude demodulation on the received signal, and then performs error correction decoding, and then performs a difference operation process according to the differential conversion method. In the digital microwave radio communication system for reproducing value digital data, the transmitting apparatus adds a frame synchronization signal having a signal pattern set in advance according to a signal point arrangement of the differential conversion method to a transmission signal and transmits the frame synchronization signal. The receiving-side device uses a signal pattern in which a frame synchronization signal sent from the transmitting-side device changes due to the phase rotation of the reproduced carrier as a comparison pattern. Leave because stored, a frame synchronization method which is characterized in that the signal pattern of the demodulated frame sync signal compared to the comparison pattern to establish the frame synchronization on the basis of the comparison result. 2. The method according to claim 1, wherein m bits for determining the amplitudes of two mutually orthogonal reference carriers are I = {I ₁ , I ₂ ,..., I _m }, Q = {Q ₁ , Q ₂ ,
.., Q _m } and two bits of the 2m bits involved in the determination of the phase quadrant of the signal point are represented by I ₁ and Q ₁ . The transmitting side device has I = {x ₁ , x ₂ , ..., x _m }, Q = {y ₁ , y ₂ , ...,
y _m } is added to the transmission signal and transmitted, and the receiving-side apparatus outputs {I ₂ , I ₃ ,..., I _m , Q out of 2m bits of the demodulated frame synchronization signal. _2, Q _3, ... comparison, the 2m-1 bit signal patterns corresponding to _{Q m}, {x 2,} x 3, ..., x m, y 2, y 3, ..., a signal pattern of y _m} 2. The frame synchronization method according to claim 1, wherein the frame synchronization is established by performing the following. 3. The method according to claim 1, wherein m bits for determining the amplitudes of two mutually orthogonal reference carriers are I = {I ₁ , I ₂ ,..., I _m }, Q = {Q ₁ , Q ₂ ,
.., Q _m }, and two bits related to the determination of the phase quadrant of the signal point among these 2 m bits are expressed as I ₁ , Q _1. The side devices are I = {x ₁ , x ₂ , ..., x _m }, Q = {y ₁ , x ₂ , ...,
x _m }, the frame synchronization signal is added to the transmission signal, and the transmission signal is transmitted. The reception-side apparatus outputs {I ₂ , I ₃ ,..., I _m , Q _2, Q _3, ..., a 2m-2 bit signal patterns corresponding to _{Q m}, {x 2,} x 3, ..., x m, x 2, 3, ..., is compared with the signal pattern of x _m} 2. The frame synchronization method according to claim 1, wherein the frame synchronization is established. 4. The method according to claim 1, wherein m bits for determining the amplitudes of two mutually orthogonal reference carriers are I = {I ₁ , I ₂ ,..., I _m }, Q = {Q ₁ , Q ₂ ,
.., Q _m }, and when 2 bits of the 2m bits involved in determining the phase quadrant of the signal point are expressed as I ₁ and Q ₁ , when the signal point arrangement is a natural binary arrangement, , The transmitting side device has I = {x ₁ , x ₂ , ..., x _m }, Q = {y ₁ , y ₂ , ...,
y _m } is added to the transmission signal and transmitted, and the receiving device demodulates as {I ₁ , I ₂ , ..., I _m , Q ₁ , Q ₂ , ..., Q _m } 2x ₁ , x ₂ , ..., x _m , y ₁ , y ₂ , ..., y _mを 1y ₁ , y ₂ ,…, y _m , ▲ ▼ , ▲ ▼,…, ▲ ▼｝ ｛▲ ▼, ▲ ▼,…, ▲▲, ▲ ▼, ▲
▼,…, ▲ ▼｝ ｛▲ ▼, ▲ ▼,…, ▲ ▼, x ₁ , x ₂ ,…, x _m比較 It is characterized by establishing frame synchronization by comparing with four kinds of signal patterns. The frame synchronization method according to claim 1, wherein 5. The method according to claim 1, wherein m bits for determining the amplitudes of two mutually orthogonal reference carriers are I = {I ₁ , I ₂ ,..., I _m }, Q = {Q ₁ , Q ₂ ,
.., Q _m }, and when 2 bits of the 2m bits involved in determining the phase quadrant of the signal point are expressed as I ₁ and Q ₁ , when the signal point arrangement is a natural binary arrangement, , The transmitting device has I = {x ₁ , x ₂ , ..., x _m }, Q = {x ₁ , x ₂ , ...,
x _m }, the transmission signal is transmitted by adding the frame synchronization signal to the transmission signal, and the receiving-side apparatus outputs an m-bit signal pattern of the frame synchronization signal demodulated as {I ₁ , I ₂ ,..., I _m }. ｛X ₁ , x ₂ ,
…, X _m ｝ and ｛▲ ▼, ▲ ▼,…, ▲ ▼｝
信号 Q ₁ , Q ₂ ,…,
The signal pattern of m bits of the frame synchronization signal demodulated as Q _m ｛is represented by ｛x ₁ , x ₂ ,..., X _m ｝ and ｛▲ ▼, ▲
3. The frame synchronization system according to claim 1, wherein the frame synchronization is established by comparing with two signal patterns of ▼,..., ▲ ▼｝.